The ADC module can generate an interrupt upon the completion of an ADC conversion. The ADC Interrupt Flag (ADIF) bit becomes set every time a conversion cycle has completed, regardless of the state of the ADC Interrupt Enable (ADIE) bit. The ADIF bit must be cleared by software.
The ADC Interrupt can be generated while the device is operating or while in Sleep mode. If the device is in Sleep mode, the interrupt will wake the device. It is important to note that the ADC can only operate in Sleep mode when the FRC is selected as the ADC clock source.