Threshold Comparison

After the ADC completes a conversion, the result is stored in the ADRES register pair. If there is a result currently in the ADRES register pair, it is transferred into the ADPREV register pair, and the new conversion result is stored in the ADRES register pair. After each sample in Basic or Accumulate modes, or once ADCNT is equal to ADRPT in Average, Burst-Average, or LPF mode, an error calculation is performed based on the configuration of the ADC Error Calculation Mode Select (CALC<2:0>) bits of the ADC Control Register 3 (ADCON3).

The Error Calculation modes include:

Depending on the Error mode selection, error calculations may involve the following registers:

The DSEN bit determines the number of conversions needed before the module begins the calculations and threshold comparison.

When DSEN is set, the module is in Double Sampling mode. Two conversion results are required before the module begins its error calculations and threshold comparison tests. If the ADC Continuous Operation Enable (CONT) bit of ADC Control Register 0 (ADCON0) is set, the ADC Conversion Status (GO) bit is held by hardware until two consecutive conversions are recorded. If the CONT bit is clear, the GO bit is cleared after each conversion, meaning that software or an external trigger must set the GO bit to trigger the second conversion.

The first conversion is loaded into the ADRES register pair, the ADC Module Computation Status (MATH) bit of the ADC Status Register (ADSTAT) is set, and the ADC Accumulator Register trio (ADACCU:ADACCH:ADACCL) is updated, but the module will not calculate the error or set the ADC Threshold Interrupt (ADTIF) bit. After the second conversion is complete, the first conversion result is transferred to the ADPREV register pair and the second result is loaded into the ADRES register pair. At this point, the error is calculated and the threshold comparison test is performed.

When DSEN is clear, a single conversion takes place each time the GO bit is set. In this case, only a single conversion is required before hardware begins the error calculation and threshold comparison. Once the new conversion is complete, the new result is stored in the ADRES register pair, and the previous conversion result is transferred to ADPREV to allow difference calculations to be performed. If CONT is set, the module will automatically reset the GO bit after each conversion. If CONT is clear, software must set GO before another conversion begins.

Once the error calculation is complete, hardware transfers the result into the ADC Error Register pair (ADERRH:ADERRL). The error is then compared to the ADC Upper Threshold Register (ADUTHH:ADUTHL) pair and the ADC Lower Threshold Register (ADLTHH:ADLTHL) pair. The threshold registers hold the user-defined threshold values that are used for error comparison. If the error value is greater than the upper threshold value, the ADC Module Greater-than Upper Threshold Flag (UTHR) bit of the ADC Status Register (ADSTAT) is set. If the error is less than the lower threshold value, the ADC Module Less-than Lower Threshold Flag (LTHR) bit of ADSTAT is set.

When a threshold comparison is made, an interrupt may be generated. The Threshold Interrupt Mode Select (TMD<2:0>) bits of ADCON3 select which interrupt condition to test for. The Interrupt modes include:

If the selected interrupt condition is met, the ADC Threshold Interrupt Flag (ADTIF) bit is set, and if the ADC Threshold Interrupt Enable (ADTIE) bit is set, an interrupt will be generated. Software must clear ADTIF.