Double sampling is enabled by setting the Double Sample Enable (DSEN) bit of the ADCON1 register. When double sampling is enabled, two consecutive conversions are acquired, and the resulting final conversion value is the difference between the second sample and the first (S2 – S1).
When Continuous Sampling mode is enabled (CONT = 1), both
conversions are completed automatically, requiring only one trigger event to capture
both conversions. The GO bit is maintained by hardware between conversion cycles, and is
cleared by hardware after both conversions are complete. When CONT = 0,
two conversion trigger events are required to capture both conversions. The GO bit is
cleared between each conversion.
The first completed conversion (S1) is written into ADRES. Once the second conversion has completed, the new (second) conversion (S2) is stored in ADRES, and if the ADC Previous Sample Input Select (PSIS) bit of ADCON2 is clear, the first completed conversion is transferred to the ADPREV register pair. If the PSIS bit is set, the ADFLTR value is loaded into ADPREV instead of the first conversion. At this point, module hardware calculates the difference between the two conversions (S2 - S1), adds the difference to the accumulator, and performs a threshold test on the updated accumulator value (except in Basic mode).