Implementation

In order to enable one-wire, two bits in the USART need to be written to ‘1’:

The Loop Back Mode Enable (LBME) bit in the CTRLA register. This bit enables the internal connection between the TXD pin and the RXD pin.
The Open-Drain Mode Enable (ODME) bit in the CTRLB register. This bit enables open-drain functionality for the TXD pin. The RXD pin will not be used by the USART.

As there needs to be at least one pull-up resistor connected to the bus, it may also be necessary to write to the respective Pull-Up Enable bit (PULLUPEN) for the pin used. The code snippet below shows how the USART is configured as a 1-Wire master in a polled mode configuration.

// Enable internal pull-up    
PORTB.PIN2CTRL = PORT_PULLUPEN_bm;
// Enable loop-back mode
USART0.CTRLA = USART_LBME_bm;
// Enable Open-drain mode. Enable TX and RX
USART0.CTRLB = USART_ODME_bm | USART_RXEN_bm | USART_TXEN_bm;
// Set 8-bit USART and 1 stop bit
USART0.CTRLC = USART_CHSIZE_8BIT_gc | USART_SBMODE_1BIT_gc;
// Set baud rate to 115200
USART0.BAUD = BAUD_115200;

If interrupts are going to be used, the Interrupt flags for data register empty and reception complete will also have to be enabled. As TXD and RXD are connected together, data transmitted will also be received. Reading out the last byte that was sent can be used as part of error checking.

If the timing of the protocol does not allow for the overhead of reading the transmitted data, either the receive interrupt or the receiver itself can be disabled while transmitting. The receive interrupt can be disabled using the Receive Complete Interrupt Enable bit (RXCIE) in the Control A register (CTRLA). The receiver can be disabled using the Receiver Enable bit (RXEN) in the Control B register (CTRLB). When receiving, the receiver and receive interrupt must be enabled.