#define SPL_PATTERN ((SPL_CONFIGURABLE_BITS_BM & 0xAAU)+ INTERNAL_SRAM_START_8LSB)Applies a checkerboard bit-pattern (0xAA) to the configurable bits of the SPL register. Because the configurable bits of SPL are dependent on the size of SRAM, it is necessary to add the start address to compensate for any non-configurable bits when reading and writing to the SPL register.