ATmega808/809/1608/1609 Errata and Clarification

ADC Performance Degrades with CLKADC Above 1.5 MHz and VDD < 2.7V

The ADC INL performance degrades if CLKADC > 1.5 MHz and ADCn.CALIB.DUTYCYC set to ‘0’ for VDD < 2.7V.

Work Around

None.

Affected Silicon Revisions

Rev. A
X
Parent topic: ADC