ATmega808/809/1608/1609 Errata and Clarification
ADC
One Extra Measurement Performed After Disabling ADC Free-Running Mode
ADC Functionality Cannot be Ensured with CLKADC Above 1.5 MHz and a Setting of 25% Duty Cycle
ADC Performance Degrades with CLKADC Above 1.5 MHz and VDD < 2.7V
Parent topic:
Silicon Errata