Port List

The following tables list the User Cryptoprocessor port list for PolarFire FPGAs and PolarFire SoC FPGAs.

Table 1. PolarFire FPGA CRYPTO Port List
Port Name Direction Description
AHB_SLAVE Bus AHB-Lite slave interface, which is used for control, and primary data input and output.
AHB_MASTER Bus AHB-Lite master DMA interface, which may optionally be used for data input and output.
DRI_SLAVE Bus Control and status signals are accessible through the DRI.
HCLK Input AHB bus clock.
HRESETN Input The reset signal, CRYPTO_HRESETN, is active low, synchronous, and is sampled on the rising edge of the clock. Asserts the functional reset of the User Cryptoprocessor block and zeroizes all the internal RAM and registers as PURGE signal. It is necessary to assert this signal for a minimum of two clock cycles to reset the core.
START Input External execution initiation input when the User Cryptoprocessor operates in the standalone configuration without a host processor connected to the bus interface. Asserting the START signal causes the User Cryptoprocessor to initiate execution. During execution, the status of the User Cryptoprocessor is reflected by the BUSY and DLL_LOCK ports. This signal must be tied low when the User Cryptoprocessor is used as a co-processor.
PURGE Input When the signal is set to '1', it initializes the Zeroization of User Cryptoprocessor internal RAM and registers. For normal operation, this signal must be tied low. The PURGE input is level sensitive, and if the PURGE pin is still asserted when a purge operation completes, another purge operation is initiated.
STALL Input Stalls the User Cryptoprocessor for a clock cycle, to introduce variance in the external signatures. The STALL input is expected to be generated by a LFSR circuit in the fabric and asserted randomly for a single cycle to achieve the required stall rates. The STALL input must not be asserted until at least three clock cycles after the HRESETN is de-asserted and the DLL has indicated LOCK for three cycles.
ALARM Output Asserted to indicate an uncorrectable memory error condition. An uncorrectable memory error causes the Crypto core to perform a reset and purge. This reset terminates any in-progress operation. For most CAL operations, the CALPKTrfRes() function is used to complete the operation and generates a hardware fault code in the event of an alarm.
BUS_ERROR Output Asserted when a HRESP response error is detected by the User Cryptoprocessor AHB master. When set, a reset is required to clear.
BUSY Output Execution status signal
COMPLETE Output Active high signal, asserted on raising edge of CRYPTO_HCLK to indicate that the User Cryptoprocessor has completed an operation. This signal can be connected to the host microprocessor as an interrupt request signal, enabling the User Cryptoprocessor to interrupt the processor when it completes an operation.
DLL_LOCK Output DLL lock status
Table 2. PolarFire SoC FPGA CRYPTO Port List 1
Port Name Direction Description
CRYPTO_AHB_SLAVE Bus AHB-Lite slave interface, which is used for control, and primary data input and output.
CRYPTO_AHB_MASTER Bus AHB-Lite master DMA interface, which may optionally be used for data input and output.
CRYPTO_HCLK Input AHB bus clock.
CRYPTO_HRESETN Input The reset signal, CRYPTO_HRESETN, is active low, synchronous, and is sampled on the rising edge of the clock. Asserts the functional reset of the User Cryptoprocessor block and zeroizes all the internal RAM and registers as PURGE signal. It is necessary to assert this signal for a minimum of two clock cycles to reset the core.
CRYPTO_GO_F2M Input External execution initiation input when the User Cryptoprocessor operates in the standalone configuration without a host processor connected to the bus interface. Asserting the GO signal causes the User Cryptoprocessor to initiate execution. During execution, the status of the User Cryptoprocessor is reflected by the BUSY and DLL_LOCK ports. This signal must be tied low when the User Cryptoprocessor is used as a co-processor.
CRYPTO_PURGE_F2M Input When the signal is set to '1', it initializes the Zeroization of User Cryptoprocessor internal RAM and registers. For normal operation, this signal must be tied low. The PURGE input is level sensitive, and if the PURGE pin is still asserted when a purge operation completes, another purge operation is initiated.
CRYPTO_STALL_F2M Input Stalls the User Cryptoprocessor for a clock cycle, to introduce variance in the external signatures. The STALL input is expected to be generated by a LFSR circuit in the fabric and asserted randomly for a single cycle to achieve the required stall rates. The STALL input must not be asserted until at least three clock cycles after the HRESETN is de-asserted and the DLL has indicated LOCK for three cycles.
CRYPTO_ALARM_M2F Output Asserted to indicate an uncorrectable memory error condition. An uncorrectable memory error causes the Crypto core to perform a reset and purge. This reset terminates any in-progress operation. For most CAL operations, the CALPKTrfRes() function is used to complete the operation and generates a hardware fault code in the event of an alarm.
CRYPTO_BUSERROR_M2F Output Asserted when a HRESP response error is detected by the User Cryptoprocessor AHB master. When set, a reset is required to clear.
CRYPTO_BUSY_M2F Output Execution status signal
CRYPTO_COMPLETE_M2F Output Active high signal, asserted on raising edge of CRYPTO_HCLK to indicate that the User Cryptoprocessor has completed an operation. This signal can be connected to the host microprocessor as an interrupt request signal, enabling the User Cryptoprocessor to interrupt the processor when it completes an operation.
CRYPTO_DLL_LOCK_M2F Output DLL lock status
CRYPTO_MESH_CLEAR_F2M Input Crypto Mesh error clear should be asserted for at least 5 ns
CRYPTO_MESH_ERROR_M2F Output Indicates that the security mesh detected an error because of wires are cut or shorted. When set, stays set until cleared.
Cryptoprocessor Ownership Handshake Interface
CRYPTO_REQUEST_F2M Input Fabric request or is using the Cryptoprocessor
CRYPTO_MSS_REQUEST_M2F Output MSS request or is using the Cryptoprocessor
CRYPTO_RELEASE_F2M Input Fabric released the Cryptoprocessor
CRYPTO_MSS_RELEASE_M2F Output MSS released the Cryptoprocessor
CRYPTO_OWNER_M2F Output Indicates that the Fabric owns the Cryptoprocessor and the fabric interface is enabled
CRYPTO_MSS_OWNER_M2F Output Indicates that the MSS owns the Cryptoprocessor and the fabric interface is disabled
CRYPTO_REQUEST_F2M Input Fabric request or is using the Cryptoprocessor
CRYPTO_MSS_REQUEST_M2F Output MSS request or is using the Cryptoprocessor
Cryptoprocessor Streaming Interface
CRYPTO_XWDATA_F2M Input Transfer in data
CRYPTO_XWADDR_M2F Output Transfer in data address output
CRYPTO_XENABLE_F2M Input Transfer in data request
CRYPTO_XINACCEPT_M2F Output Transfer in data accept
CRYPTO_XRDATA_M2F Output Transfer out data
CRYPTO_XRADDR_M2F Output Transfer out data address output
CRYPTO_XVALIDOUT_M2F Output Transfer out data valid output
CRYPTO_XOUTACK_F2M Input Transfer out data acknowledgment
Note: 1. Input refers to an input port to MSS from Fabric and output refers to an output port from MSS to Fabric.