JTAG Security Monitor

The UJTAG_SEC macro, available in the Libero Catalog, allows a user-defined security monitor implemented in the FPGA fabric to observe all the JTAG signal activity. It also enables control of the System Controller TDI and the TRSTB inputs.

Figure 1. UJTAG_SEC
Table 1. UJTAG_SEC Ports and Descriptions
Port Direction Polarity Description
UIREG[7:0] Output This 8-bit bus carries the contents of the JTAG instruction register of each device. The instruction values, from 16 to 127, are not reserved and can be employed as user-defined instructions.
URSTB Output Low URSTB is an active-low signal and is asserted when the TAP controller is in the Test-Logic-Reset mode. URSTB is asserted at power-up, and a power-on reset signal resets the TAP controller state.
UTDI Output Directly connected to the TAP's TDI signal.
UDRSH Output High Active-high signal enabled in the Shift_DR TAP state.
UDRCAP Output High Active-high signal enabled in the Capture_DR_TAP state.
UDRCK Output Directly connected to the TAP's TCK signal.

Note: UDRCK must be connected to a global macro such as CLKINT. If this is not done, Synthesis/Compile will add it to the netlist to legalize it.

UDRUPD Output High Active-high signal enabled in the Update_DR_TAP state.
TDO Output Test Data Out. Serial output for JTAG boundary scan. The TDO pin does not have an internal pull-up/pull-down resistor.
TDO Output Test Data Out. Serial output for JTAG boundary scan. The TDO pin does not have an internal pull-up/pull-down resistor.
UTDO Input User TDO output. Inputs to the UTDO port are sent to the TAP TDO output MUX when the IR address is in user range.
TCK Input Test Clock. Serial input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-up/pull- down resistor.

Connect TCK to GND or +3.3 V through a resistor (500 - 1 KΩ) placed closed to the FPGA pin to prevent totem-pole current on the input buffer and TMS from entering into an undesired state.

If JTAG is not used, connect it to GND.

TDI Input Test Data In. Serial input for JTAG boundary scan. There is an internal weak pull-up resistor on the TDI pin.
TMS Input Test mode select. The TMS pin controls the use of the IEEE 1149.1 boundary scan pins (TCK, TDI, TDO, and TRST). There is an internal weak pull-up resistor on the TMS pin.
TRSTB Input Low Test reset. The TRSTB pin is an active low input. It synchronously initializes (or resets) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRSTB pin.

To hold the JTAG in reset mode and prevent it from entering into undesired states in critical applications, connect TRSTB to GND through a 1 KΩ resistor (placed close to the FPGA pin).

EN_SEC Input High Enable Security. Enables the user design to override the external TDI and TRSTB input to the TAP. Tie LOW in the design when not used.
TDI_SEC Input TDI Security override. Overrides the external TDI input to the TAP when SEC_EN is HIGH.
TRSTB_SEC Input Low TRSTB Security override. Overrides the external TRSTB input to the TAP when SEC_EN is HIGH.
Note: When the JTAG Security Monitor interface is enabled, the maximum TCK frequency for the device may be limited by delays through the user logic. TCK frequency is not monitored by the device as no security sensitive logic operates in this clock domain. When the FPGA fabric is powered down, the Security Monitor interface is disabled.