Reset Reason

RESET_REASON[4:0] is a 5-bit field compressed from a 14-bit reset reason register, see Table 1 for bit definitions. This field is intended to provide the FPGA fabric a general cause of device reset. To determine the exact reset reason, the user must read the RESET_REASON[13:0] register using the Read Debug System Service. For information about this register and the service, see ®PolarFireFPGA and PolarFire SoC FPGA System Services User Guide. When the System Controller Suspend Mode feature is enabled, RESET_REASON[4:0] is updated only at FPGA initialization. To prevent loss of the reset reason when using this feature, these outputs should be latched by enabling the Latch System Controller outputs option in the Tamper macro.

Table 1. Reset Reason
Reset Reason Description

This field indicates to the user the reason for the most recent reset of the System Controller. The bits are allocated as follows:

[0]: Device is reset through the DEVRSTN pin

[1]: Device reset through tamper response input

[2]: System Controller's Watchdog had triggered the reset

[3]: Reset due to security locks system detected a security issue

[4]: Any other reset