MSS Cryptoprocessor Configuration Registers

The Cryptoprocessor includes three APB mapped registers that are used to configure the Cryptoprocessor and control the ownership from the MSS side.

Table 1. MSS Crypto Registers
Offset from 0x20127000 Register Name
0x00 MSS Crypto Control register
0x04 MSS Crypto stall seed register
0x08 MSS Crypto address upper register
Table 2. MSS Crypto Control Register
Bits Type Field Reset Description
0 RW RESET 1 Asserts the internal Crypto core reset signal
1 RW PURGE 0 Asserts the Crypto core purge command input
2 RW GO 0 Asserts the Crypto core go input
3 RW RING_OSC_ON 0 Turns on the Crypto core ring oscillators, note turned off at reset
4 RW STREAM_ENABLE 0 Enables the streaming interface to the fabric
5 RW STALL_ENABLE 0 Enables the stall system on the Crypto core

0: Operates in Fabric mode using fabric stall signal

1: Internal mode enabled

7:6 RW STALL_RATE 0 Sets the average stall rate used in internal mode

00: 1 in 8

01: 1 in 16

10: 1 in 32

11: 1 in 64

8 RW COMPLETE 0 Status signal from Crypto core indicating complete
9 RO ALARM 0 Status signal from Crypto core indicating alarm condition
10 RO BUSERROR 0 Status signal from Crypto core indicating it received an AHB bus error response
11 RO STREAM_ENABLED 0 Indicates that the streaming interface is enabled
12 RO BUSY 0 Status signal from Crypto core indicating busy
15:13 RO RESERVED 0 Reads as zero
16 RW USE_FAB_CLK 0 Forces the block to use the fabric sourced clock when in MSS mode, allowing the streaming interface to operate concurrently with MSS access the AHB buses.
23:17 RO RESERVED 0 Reads as zero
24 RW MSS_REQUEST 0 MSS requests Crypto core use
25 RW MSS_RELEASE 0 MSS releases Crypto core
26 RO FAB_REQUEST 0 Fabric is requesting Crypto core use
27 RO FAB_RELEASE 0 Fabric is requesting Crypto core use
28 ROR MSS_OWNER 0 MSS controls the Crypto core
29 RO FAB_OWNER 0 Fabric controls the Crypto core
31:30 RO RESERVED 0 Reads as zero
Table 3. MSS Crypto Stall Seed Register
Bits Type Field Reset Description
31:0 RW SEED 0 Sets the 32-bit seed value used by the Crypto core stall logic. Any 32-bit value should be used, ideally a random value at each device boot.
Table 4. MSS Crypto Address Upper Register
Bits Type Field Reset Description
5:0 RW UPPER_ADDR 0 Sets the upper six bits [37:32] of the Address used by the Crypto AHB master, allows the 32-bit Crypto core to interface to the full 38-bit MSS system