Cryptoprocessor Stall System

The Cryptoprocessor incorporates a stall system that allows the clock to the Cryptoprocessor core to have clock pulses suppressed in a pseudo random way. This makes the internal operations of the Crypto core harder to infer from external observations. The stall cycles cannot occur during an active AHB cycle and occurs as soon as the AHB buses are idle.

User Cryptoprocessor has a STALL input in PolarFire FPGAs by default. This input is available in Fabric, Shared-MSS and Shared-Fabric modes of PolarFire SoC FPGAs. The STALL input from fabric is expected to be generated by a LFSR circuit in the fabric and asserted randomly for a single cycle to achieve the required stall rates. The STALL input must be synchronous to the Cryptoprocessor clock sourced from the fabric. The STALL input must not be asserted until at least three clock cycles after the HRESETN is de-asserted and the DLL has indicated LOCK for three cycles.

In PolarFire SoC FPGA, there is an internal stall generator, which can be enabled or disabled through MSS Crypto Control Register. A 32-bit seed value is provided for initializing the random generator through MSS Crypto Stall Seed Register. It is recommended to set this to a random value on each device reset. When the configuration stall enable bit is set, stall operation is also enabled on the MSS AHB interface using a pseudo-random generator to insert a stall cycle on average of every 8, 16, 32 or 64 clock cycles depending on the set rate in MSS Crypto Control Register.

The internal stall generator can also be used in Fabric mode. In this case, stall cycles are inserted by the internal generator and the stall signal from the fabric.