Direct Transfer Output

The DXO instruction copies a block of data to the direct transfer output port, CRYPTO_XRDATA_M2F, from the source register. The source register address and length of the transfer is specified in the DXO instruction. Transfers are controlled by the CRYPTO_XVALIDOUT_M2F/CRYPTO_XOUTACK_F2M handshake, and the DXO instruction runs until the specified number of words are transferred.

The DXO instruction will not complete until the specified number of words have been transferred. If the specified number of words of data are never accepted, then the instruction will never complete.

On the rising edge of CRYPTO_HCLK, data is presented on CRYPTO_XRDATA_M2F, and the CRYPTO_XVALIDOUT_M2F signal is asserted. The receiving party indicates receipt of the data by asserting the CRYPTO_XOUTACK_F2M signal, which is sampled on the rising edge of CRYPTO_HCLK by the Cryptoprocessor. The CRYPTO_XOUTACK_F2M signal may be asserted on the same clock cycle that CRYPTO_XVALIDOUT_M2F is asserted or any subsequent clock cycle. The waveform in the following figure shows an example where the CRYPTO_XOUTACK_F2M is asserted one cycle after CRYPTO_XVALIDOUT_M2F is asserted. If CRYPTO_XVALIDOUT_M2F is negated, the CRYPTO_XOUTACK_F2M signal is ignored.

Figure 1. Direct Transfer Output Signal Waveforms

If the direct transfer output port is not used, the CRYPTO_XOUTACK_F2M signal must be tied high. If the CRYPTO_XOUTACK_F2M signal is tied low, any use of the DXO instruction causes the Cryptoprocessor to halt, since the DXO instruction blocks until the transfer is complete. Recovery in this case requires a reset.