Memory Protection Unit (For PolarFire SoC FPGA Only)

Random access to memory regions by any non-CPU master can corrupt the memory and the overall system. To avoid random access to memory, the PolarFire SoC MSS includes a built-in Memory Protection Unit (MPU) for each non-CPU master. The GEM0, GEM1, eMMC, USB, SCB, Crypto Processor, Trace, FIC0, FIC1, and FIC2 master blocks interface with an MPU. The MPU can be used to create access regions in memories for a particular master and define privileges to those access regions. The access regions are created by setting the PMP registers inside an MPU. The privileges are also defined by setting particular bits of the PMP registers. At reset, access to the MSS is not provided until the access regions of the required MPUs are created.

MPUs monitor transactions on the AXI read and write channels and only legal accesses pass through. Illegal transactions are not allowed to pass from MPU to the AXI switch, and the MPU initiates AXI response transaction. For more information, see PolarFire SoC FPGA MSS Technical Reference Manual.