Direct Transfer Input

The DXI instruction allows to copy a block of data from the streaming interface input port, CRYPTO_XWDATA_F2M, to a destination register. The destination register address and length of the transfer is specified in the DXI instruction. Transfers are controlled by the CRYPTO_XENABLE_F2M/CRYPTO_XINACCEPT_M2F handshake, and the DXI instruction will run until the specified number of words have been transferred. The DXI instruction will not complete until the specified number of words have been transferred. If the specified number of words of data never arrive, then the instruction will never complete.

If the direct transfer input port is not used, the CRYPTO_XENABLE_F2M signal should be tied high and the CRYPTO_XWDATA_F2M signal should be tied to a known value.

The transmitting party drives CRYPTO_XWDATA_F2M and asserts CRYPTO_XENABLE_F2M. The Cryptoprocessor indicates that it will accept the data on the next rising edge of CRYPTO_HCLK by asserting the CRYPTO_XINACCEPT_M2F signal. If the CRYPTO_XINACCEPT_M2F signal is negated, then the CRYPTO_XENABLE_F2M and CRYPTO_XWDATA_F2M inputs will be ignored by the Cryptoprocessor. The waveform in the following figure shows an example of a case where data is presented for input to the Cryptoprocessor and accepted in the same clock cycle.

Figure 1. Direct Transfer Input Signal Waveforms

If the CRYPTO_XENABLE_F2M signal is tied low, any use of the DXI instruction can cause the Cryptoprocessor to halt, since the DXI instruction blocks until the transfer is complete. Recovery in this case requires a reset.