User Debug Security Locks

The debugging features can be deactivated using the user debug lock bits. These lock bits enable the following:

Table 1. Locks to Control Debug Access
Lock Function when Active Description
Disable user debug access and active probes SmartDebug user debug access and active probes are disabled on both JTAG and SPI slave interfaces.
Disable live probes SmartDebug Live probe debug access is disabled on both JTAG and SPI slave interfaces.
Disable sNVM SmartDebug sNVM debug access is disabled on both JTAG and SPI slave interfaces.
Disable UJTAG command through JTAG interface Disables the UJTAG interface to the FPGA fabric by asserting the URSTB fabric input, holding the associated user logic in reset. All other signals on the UJTAG interface continue to operate as normal allowing the interface to continue to be used for monitoring functions. Libero catalog includes a UJTAG macro to access UJTAG interface.
Disable JTAG (1149.1) boundary scan JTAG (1149.1) boundary scan is disabled. The following JTAG instructions will be disabled: EXTEST, INTEST, CLAMP, SAMPLE, and PRELOAD. I/Os will be tristated when in JTAG programming mode and BSR control during programming is disabled. BYPASS, IDCODE, and USERCODE instructions will remain functional.
Disable reading temperature and voltage sensor (JTAG/SPI Slave) Reading of temperature and voltage sensor is disabled on both JTAG and SPI slave interfaces.

Use FlashLock/UPK1 or DPK to temporarily enable access to the disabled debug features during one debug session. It stays in effect only until the device is reset or power cycled. DPK unlocks just certain lock bits related to FPGA debugging, but does not unlock as many lock bits as the FlashLock passcode does. For example, it does not allow the user to overwrite any keys, passcodes, or security settings.

In the Configure Security Wizard, click Debug policy to lock the debugging features, as shown in the following figure.

Figure 1. Debug Policy Page in Configure Security Wizard