PIR1
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCP1IF | TMR2IF | TMR1IF | RC1IF | TX1IF | BCL1IF | SSP1IF | ADIF |
AccessR/W/HS | R/W/HS | R/W/HS | R | R | R/W/HS | R/W/HS | R/W/HS |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
CCP1 Interrupt Flag
Value | CCP Mode | ||
---|---|---|---|
Capture | Compare | PWM | |
1 |
Capture occurred (must be cleared in software) | Compare match occurred (must be cleared in software) | Output trailing edge occurred (must be cleared in software) |
0 |
Capture did not occur | Compare match did not occur | Output trailing edge did not occur |
TMR2 Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared in software) |
0 | Interrupt event has not occurred |
TMR1 Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared in software) |
0 | Interrupt event has not occurred |
EUSART1 Receive Interrupt Flag(1)
Value | Description |
---|---|
1 | The EUSART1 receive buffer (RC1REG) is not empty (contains at least one byte) |
0 | The EUSART1 receive buffer is empty |
EUSART1 Transmit Interrupt Flag(2)
Value | Description |
---|---|
1 | The EUSART1 transmit buffer (TX1REG) is empty |
0 | The EUSART1 transmit buffer is not empty |
MSSP1 Bus Collision Interrupt Flag
Value | Description |
---|---|
1 | A bus collision was detected (must be cleared in software) |
0 | No bus collision was detected |
MSSP1 Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared in software) |
0 | Interrupt event has not occurred |
ADC Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared in software) |
0 | Interrupt event has not occurred |