Pin Allocation Tables

Table 1. 8-Pin Allocation Table
I/O	8-Pin PDIP SOIC DFN	ADC	Reference	Timers	CCP	10-Bit PWM	MSSP	EUSART	IOC	Interrupt	Basic
RA0	7	ANA0	—	—	—	—	—	CK1^(1,3)	IOCA0	—	ICSPDAT ICDDAT
RA1	6	ANA1	V_REF+ (ADC)	—	—	—	SCL1^(1,3) SCK1^(1,3)	RX1⁽¹⁾ DT1^(1,3)	IOCA1	—	ICSPCLK ICDCLK
RA2	5	ANA2	—	T0CKI⁽¹⁾	—	—	SDA1^(1,3) SDI1^(1,3)	—	IOCA2	INT⁽¹⁾	—
RA3	4	—	—	—	—	—	SS1⁽¹⁾	—	IOCA3	—	MCLR V_PP
RA4	3	ANA4	—	T1G⁽¹⁾	—	—	—	—	IOCA4	—	CLKOUT
RA5	2	ANA5 ADACT⁽¹⁾	—	T1CKI⁽¹⁾ T2IN⁽¹⁾	CCP1⁽¹⁾ CCP2⁽¹⁾	—	—	—	IOCA5	—	CLKIN
V_DD	1	—	—	—	—	—	—	—	—	—	V_DD
V_SS	8	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	—	TMR0	CCP1 CCP2	PWM3 PWM4	SCL1 SCK1 SDA1 SDO1	TX1 DT1 CK1	—	—	—
Notes: 1.This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin. 2.All output signals shown in this row are PPS remappable. 3.This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.

Table 2. 14/16-Pin Allocation Table
I/O	14-Pin PDIP SOIC TSSOP	16-Pin QFN	ADC	Reference	Timers	CCP	10-Bit PWM	MSSP	EUSART	IOC	Interrupt	Basic
RA0	13	12	ANA0	—	—	—	—	—	—	IOCA0	—	ICSPDAT ICDDAT
RA1	12	11	ANA1	V_REF+ (ADC)	—	—	—	—	—	IOCA1	—	ICSPCLK ICDCLK
RA2	11	10	ANA2	—	T0CKI⁽¹⁾	—	—	—	—	IOCA2	INT⁽¹⁾	—
RA3	4	3	—	—	—	—	—	—	—	IOCA3	—	MCLR V_PP
RA4	3	2	ANA4	—	T1G⁽¹⁾	—	—	—	—	IOCA4	—	CLKOUT
RA5	2	1	ANA5	—	T1CKI⁽¹⁾ T2IN⁽¹⁾	—	—	—	—	IOCA5	—	CLKIN
RC0	10	9	—	—	—	—	—	SCL1^(1,3,4) SCK1^(1,3,4)	—	IOCC0	—	—
RC1	9	8	—	—	—	—	—	SDA1^(1,3,4) SDI1^(1,3,4)	—	IOCC1	—	—
RC2	8	7	ANC2 ADACT⁽¹⁾	—	—	—	—	—	—	IOCC2	—	—
RC3	7	6	ANC3	—	—	CCP2⁽¹⁾	—	SS1⁽¹⁾	—	IOCC3	—	—
RC4	6	5	ANC4	—	—	—	—	—	CK1^(1,3)	IOCC4	—	—
RC5	5	4	ANC5	—	—	CCP1⁽¹⁾	—	—	RX1⁽¹⁾ DT1^{(1, 3)}	IOCC5	—	—
V_DD	1	16	—	—	—	—	—	—	—	—	—	V_DD
V_SS	14	13	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	—	—	TMR0	CCP1 CCP2	PWM3 PWM4	SCL1 SCK1 SDA1 SDO1	TX1 DT1 CK1	—	—	—
Notes: 1.This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin. 2.All output signals shown in this row are PPS remappable. 3.This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. 4.These pins can be configured for I²C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.

Table 3. 20-Pin Allocation Table
I/O	20-Pin PDIP SOIC SSOP	20-Pin VQFN	ADC	Reference	Timers	CCP	10-Bit PWM	MSSP	EUSART	IOC	Interrupt	Basic
RA0	19	16	ANA0	—	—	—	—	—	—	IOCA0	—	ICSPDAT ICDDAT
RA1	18	15	ANA1	V_REF+ (ADC)	—	—	—	—	—	IOCA1	—	ICSPCLK ICDCLK
RA2	17	14	ANA2	—	T0CKI⁽¹⁾	—	—	—	—	IOCA2	INT⁽¹⁾	—
RA3	4	1	—	—	—	—	—	—	—	IOCA3	—	MCLR V_PP
RA4	3	20	ANA4	—	T1G⁽¹⁾	—	—	—	—	IOCA4	—	CLKOUT
RA5	2	19	ANA5	—	T1CKI⁽¹⁾ T2IN⁽¹⁾	—	—	—	—	IOCA5	—	CLKIN
RB4	13	10	—	—	—	—	—	SCL1^(1,3,4) SCK1^(1,3,4)	—	IOCB4	—	—
RB5	12	9	ANB5	—	—	—	—	—	RX1⁽¹⁾ DT1^(1,3)	IOCB5	—	—
RB6	11	8	ANB6	—	—	—	—	SDA1^(1,3,4) SDI1^(1,3,4)	—	IOCB6	—	—
RB7	10	7	ANB7	—	—	—	—	—	CK1^(1,3)	IOCB7	—	—
RC0	16	13	—	—	—	—	—	—	—	IOCC0	—	—
RC1	15	12	—	—	—	—	—	—	—	IOCC1	—	—
RC2	14	11	ANC2 ADACT⁽¹⁾	—	—	—	—	—	—	IOCC2	—	—
RC3	7	4	ANC3	—	—	CCP2⁽¹⁾	—	—	—	IOCC3	—	—
RC4	6	3	ANC4	—	—	—	—	—	—	IOCC4	—	—
RC5	5	2	ANC5	—	—	CCP1⁽¹⁾	—	—	—	IOCC5	—	—
RC6	8	5	—	—	—	—	—	SS1⁽¹⁾	—	IOCC6	—	—
RC7	9	6	—	—	—	—	—	—	—	IOCC7	—	—
V_DD	1	18	—	—	—	—	—	—	—	—	—	V_DD
V_SS	20	17	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	—	—	TMR0	CCP1 CCP2	PWM3 PWM4	SCL1 SCK1 SDA1 SDO1	TX1 DT1 CK1	—	—	—
Notes: 1.This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin. 2.All output signals shown in this row are PPS remappable. 3.This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. 4.These pins can be configured for I²C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.