The XMEGA Clock System provides two Digital Frequency-locked Loops (DFLLs), one for the 2MHz RC oscillator and one for the 32MHz ring oscillator. The DFLLs can be configured individually to use either the internal 32kHz RC oscillator or an external 32kHz watch crystal as a reference for the calibration process.
Once enabled, a DFLL provides continuous calibration of its oscillator based on the clock reference. When entering sleep mode, the current state is frozen and the calibration loop continues from where it stopped when exiting from sleep mode again.
If a DFLL is disabled, the current calibration value for the oscillator will remain in effect until the DFLL is enabled again and the calibration process continues.
The DFLL Control register (OSC.DFLLCTRL) contains two control bits, DFLL 32MHz Calibration Reference Selection (R32MCREF) and DFLL 2MHz Calibration Reference Selection (RC2MCREF), which select the clock reference for the DFLLs. A logic zero selects the internal 32kHz RC oscillator, while a logic one selects the external watch crystal oscillator. Hardware will disregard any attempts to use an unstable clock source.
The DFLLs themselves require a three-byte counter reference value in the corresponding DFLL Counter registers (OSC.DFLLx.OSCCNTn). Correct counter reference values are loaded automatically on reset and should not be changed by the user.
The DFLLs also have a two-byte calibration register each (OSC.DFLLx.CALn), which contains an enable bit and a calibration value, which is loaded automatically by hardware on reset. The calibration value serves as a starting point for the calibration loop and should not be changed by the user.
The correct procedure for enabling a DFLL is as follows:
There are no runtime calibration options for the internal 32kHz RC oscillator, but if required, it can be fine-tuned by changing its calibration register (RC32KCAL). However, great care should be taken not to tune any oscillator outside recommended operating limits.