High-frequency PLL Option

If higher frequencies are required, a built-in PLL can be used to multiply a clock source by a factor from 1 to 31. The following clock sources can be used as input to the PLL:

The hardware will not allow using the external oscillator as a PLL source if it is configured for 32kHz operation. If the external clock is used as input, it must be above 0.4MHz. Refer to the electrical characteristics for accurate minimum values.

The correct procedure for enabling the PLL is as follows:

  1. 1.Select multiplication factor using the Multiplication Factor bitfield (PLLFAC) and input clock source using the Clock Source bitfield (PLLSRC) in the PLL Control Register (OSC.PLLCTRL).
  2. 2.Enable the PLL using the PLL Enable bit (PLLEN) in the Oscillator Control register (OSC.CTRL).
  3. 3.Wait for the PLL to stabilize by checking the PLL Ready bit (PLLRDY) in the Oscillator Status register (OSC.STATUS).

The user should make sure that the input clock source is stable before trying to enable the PLL. When enabled, the PLL typically needs 64 reference cycles to stabilize.

The PLL configuration cannot be changed without disabling it first. Hardware will disregard any attempts to change the configuration while it is enabled.

The user is responsible for providing a minimum input clock frequency to the PLL and make sure that the output never exceeds 200MHz. The minimum input frequency requirement applies when using an external clock signal as input to the PLL.