Contents
2. Silicon Issue Summary
3. Silicon Errata Issues
3.1. Module: ADCC - Analog-to-Digital Converter with Computation
3.1.1. ADC Conversion
3.1.2. ADCRC Oscillator Operation in Sleep
3.1.3. Missing Codes with FVR Reference
3.1.4. ADC GO Bit May Remain Set When the Clock Source is FOSC
3.1.5. ADCC Burst Average Mode
3.1.6. Double Sample Conversions
3.1.7. ADC Conversion Acquisition Time in Sleep (ADCC)
3.1.8. ADC Short in Pre-Charge State
3.2. Module: PIC18 Debug Executive
3.2.1. Data Write Match Breakpoints
3.2.2. Single Step function does not execute at SW Breakpoint.
3.3. Module: PIC18 Core
3.3.1. TBLRD Requires NVMREG Value to Point to Appropriate Memory
3.4. Module: Program Flash Memory (PFM)
3.4.1. Endurance of PFM is Lower than Specified
3.4.2. PFM Back to Back Writes
3.5. Module: MSSP
3.5.1. SMBus 2.0 Voltage Level
3.5.2. MSSP SPI Client Mode
3.5.3. SMBus 2.0 Voltage Level
3.6. Module: Electrical Specifications
3.6.1. Min VDD Specification (LF Devies Only)
3.6.2. FVR - Fixed Voltage Reference
3.6.3. ADC - Analog-to-Digital Converter
3.7. Module: Timer0
3.7.1. Synchronous mode
3.8. Module: Windowed Watchdog Timer (WWDT)
3.8.1. Window Operation in Doze Mode
3.9. Module: Nonvolatile Memory (NVM)
3.9.1. NVMERR
3.10. Module: SMT
3.10.1. Reset Bit
3.11. Module: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
3.11.1. Double Byte Transmit
3.12. Module: Capture/Compare/PWM Module (CCP)
3.12.1. Wrong Duty Cycle for CCP Module
3.13. Module: Low-Voltage In-Circuit Serial Programming (LVP)
3.13.1. Low-Voltage Programming Not Possible
4. Data Sheet Clarifications
4.1. Module: Electrical Specifications
4.1.1. ADC Offset Error
5. Appendix A: Revision History
6. Microchip Information
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