H.264 Encoder is implemented in the PolarFire SoC FPGA (MPFS250T-1FCG1152I package) and generates compressed data by using 4:2:2 sampling of input data.
| Resource | Usage |
|---|---|
| 4 Look-Up Tables (LUTs) | 69092 |
| D Flip Flops (DFFs) | 65522 |
| Static Random Access Memory (LSRAM) | 232 |
| uSRAM | 30 |
| Math blocks | 19 |
| Interface 4-input LUTs | 9396 |
| Interface DFFs | 9396 |