Ports

The following tables list the description of the input and the output ports of the H.264 Encoder.

Table 1. Inputs and Outputs of H.264 Encoder
Signal Name  Direction Width Description
DDR_CLK_I Input 1 DDR memory controller clock
PIX_CLK_I Input 1 Input clock with which incoming pixels are sampled
RESET_N Input 1 Active-low Asynchronous reset signal to the design
DATA_VALID_I Input 1 Input Pixel data valid signal
DATA_Y_I Input 8 8-bit Luma pixel input in 422 format
DATA_C_I Input 8 8-bit Chroma pixel input in 422 format
FRAME_START_I Input 1 Start of Frame indication

The rising edge of this signal is considered as frame start.
FRAME_END_I Input 1 End of Frame indication
DDR_FRAME_START_ADDR_I Input 8 DDR memory start address (LSB 24-bits are 0) to store the reconstructed frame. The H.264 IP will store 4 frames and it will use 64 MB of DDR memory.
I_FRAME_FORCE_I Input 1 User can force to I frame at anytime. It is pulse signal.
PCOUNT_I Input 8 Number of P frames per every I frame

422 format value ranges from 0 to 255.
QP Input 6 Quality factor for H.264 quantization

422 fornat value ranges from 0 to 51 where 0 represents highest quality and lowest compression and 51 represents highest compression.
SKIP_THRESHOLD_I Input 12 Threshold for skip block decision

This value represents the SAD value of 16 x 16 Macro block for skipping. The range is from 0 to 1024, with a typical value of 512. Higher threshold produces more skip blocks and low quality.
VRES_I Input 16 Vertical resolution of input image. It must be multiple of 16.
HRES_I Input 16 Horizontal resolution of input image. It must be multiple of 16.
DATA_VALID_O Output 1 Signal denoting encoded data is valid. 
DATA_O Output 16 H.264 encoded data output that contains NAL unit, slice header, SPS, PPS, and the encoded data of macro blocks. 
WRITE_ CHANNEL_BUS — — Write channel bus to be connected with Video arbiter Write channel bus. This is available when the bus interface is selected for Arbiter Interface.
READ_CHANNEL_BUS — — Read channel bus to be connected with Video arbiter Read channel bus. This is available when the bus interface is selected for Arbiter Interface.
DDR Write Native IF—These ports are available when the Native interface is selected for Arbiter Interface.
DDR_WRITE_ACK_I Input 1 Write acknowledgment from arbiter write channel.
DDR_WRITE_DONE_I Input 1 Write completion from arbiter.
DDR_WRITE_REQ_O Output 1 Write request to arbiter.
DDR_WRITE_START_ADDR_O Output 32 DDR address to which write has to be made.
DDR_WBURST_SIZE_O Output 8 DDR write burst size.
DDR_WDATA_VALID_O Output 1 Data valid to arbiter.
DDR_WDATA_O Output DDR_AXI_DATA_WIDTH Data output to arbiter.
DDR Read Native IF—These ports are available when the Native interface is selected for Arbiter Interface.
DDR_READ_ACK_I Input 1 Read acknowledgment from arbiter read channel.
DDR_READ_DONE_I Input 1 Read completion from arbiter.
DDR_RDATA_VALID_I Input 1 Data valid from arbiter.
DDR_RDATA_I Input DDR_AXI_DATA_WIDTH Data input from arbiter.
DDR_READ_REQ_O Output 1 Read request to arbiter.
DDR_READ_START_ADDR_O Output 32 DDR address from which read has to be made.
DDR_RBURST_SIZE_O Output 8 DDR read burst size.
Parent topic: Inputs and Outputs