SPI Interface

The SPI source streams the raw values received on the SPI interface.

Important: The SPI hardware module uses an active-low Chip Select (CS) signal. Any data sent when the CS pin is high will be ignored.

The SPI interface is under the DGI section of the Data Sources (left) pane. When an SPI connection is selected, the SPI settings are displayed in the lower section of this pane.

Table 1. SPI Settings
Field Name	Values	Usage
Char Length	5, 6, 7, or 8 bits	Number of bits in each transfer
Mode	Clock idle normally low, Sample data on rising edge Clock idle normally low, Sample data on falling edge Clock idle normally high, Sample data on falling edge Clock idle normally high, Sample data on rising edge	SPI mode, controlling clock phase and sampling.
Force CS Sync	Check to enable.	The SPI interface is only enabled after the Chip Select line has toggled twice.
Kit-side Timestamping	Check to enable.	Target timestamping