Interfacing SERDES (PCIe) with the Initialization Logic

To interface SERDES with the initialization logic:
  1. 1.
  2. 2. Build the initialization circuitry for the SERDES (PCIe) core.
  3. 3. Drag and drop the generated SERDES (PCIe) component from the Design Hierarchy window into the top level SmartDesign canvas.
  4. 4. Drag and drop the SmartDesign component pcie_init from the Design Hierarchy window into the same SmartDesign canvas where you instantiated the SERDES component.
  5. 5. To interface the NPSS_SERDES to the initialization logic block pcie_init, make the following connections between the pcie_init block and your PCIe SERDES block in the SmartDesign.

    6. Port/Bus Interface (BIF) of SERDES Block Port/Bus Interface (BIF) Name/Block
    APB_SLAVE/SERDES block INIT_APB/Init Block
    APB_S_PCLK/SERDES block INIT_CLK/Init Block
    PHY_RESET_N/SERDES block PHY_RESET_N/Init Block
    CORE_RESET_N/SERDES block CORE_RESET_N/Init Block
    APB_S_PRESET_N/ SERDES block INIT_RESET_N/Init Block
    SPLL_LOCK/SERDES block SPL_LOCK/Init Block
    PCIE_L2P2_ACTIVE/SERDE S block Can be used to connect to Hot Reset and L2 Exit detection logic if implemented.

  6. 6. When completed, click the Generate button in SmartDesign to generate the PCIe SERDES subsystem.
    Figure 1. PCIe Subsystem Initialization Circuitry


    This completes the procedure for the SERDES (PCIe) high-speed serial interface initialization.

Parent topic: PCIe Cores