In Transmit mode, TWDR contains the next
byte to be transmitted. In Receive mode, the TWDR contains the last byte received. It is
writable while the TWI is not in the process of shifting a byte. This occurs when the
TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Register cannot be
initialized by the user before the first interrupt occurs. The data in TWDR remains
stable as long as TWINT is set. While data is shifted out, data on the bus is
simultaneously shifted in. TWDR always contains the last byte present on the bus, except
after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of
TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the
transition from Master to Slave. Handling of the ACK bit is controlled automatically by
the TWI logic, the CPU cannot access the ACK bit directly.
TWI
Data
These eight bits constitute the next data byte to be transmitted, or
the latest data byte received on the 2-wire Serial Bus.