The Store Program Memory Control and Status Register contains the control bits needed
to control the Program memory operations.
When addressing I/O Registers as data space using LD
and ST instructions, the provided offset must be used. When using the I/O specific
commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset
within 0x00 - 0x3F.
SPM Interrupt
Enable
When the SPMIE bit
is written to '1', and the I-bit in the Status Register is set ('1'), the SPM ready
interrupt will be enabled. The SPM ready Interrupt will be executed as long as the
SPMEN bit in the SPMCSR Register is cleared (SPMCSR.SPMEN). The interrupt will not
be generated during EEPROM write or SPM.
Read-While-Write Section Busy
This bit is for
compatibility with devices supporting Read-While-Write. It will always read as
zero.
Signature Row Read
If this bit is
written to one at the same time as SPMEN, the next LPM instruction within three
clock cycles will read a byte from the signature row into the destination register.
Please refer to Reading the Signature Row from Software. An SPM instruction
within four cycles after SIGRD and SPMEN are set will have no effect. This operation
is reserved for future use and should not be used.
Read-While-Write Section Read Enable
The functionality of this bit in ATmega48PB is
a subset of the functionality in ATmega88PB and
ATmega168PB. If the RWWSRE bit is
written while filling the temporary page buffer, the temporary page buffer will be
cleared and the data will be lost.
Boot Lock Bit Set
The functionality of this bit in ATmega48PB is
a subset of the functionality in ATmega88PB and
ATmega168PB. An LPM instruction within
three cycles after BLBSET and SPMEN are set in the SPMCSR Register, will read either
the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the
destination register. Please refer to
Reading the Fuse and Lock Bits from Software
Page Write
If this bit is written to one at the same time as SPMEN, the next
SPM instruction within four clock cycles executes Page Write, with the data stored
in the temporary buffer. The page address is taken from the high part of the
Zpointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon
completion of a Page Write, or if no SPM instruction is executed within four clock
cycles. The CPU is halted during the entire Page Write
operation.
Page Erase
If this bit is written to one at the same time as SPMEN, the next
SPM instruction within four clock cycles executes Page Erase. The page address is
taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The
PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction
is executed within four clock cycles. The CPU is halted during the entire Page Write
operation.
Store Program Memory
This bit enables the SPM instruction for the next four clock cycles. If written
to one together with either RWWSRE, BLBSET, PGWRT, or PGERS, the following SPM
instruction will have a special meaning, see description above. If only SPMEN is
written, the following SPM instruction will store the value in R1:R0 in the
temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is
ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or
if no SPM instruction is executed within four clock cycles. During Page Erase
and Page Write, the SPMEN bit remains high until the operation is completed.
Writing any other combination than “0x10001”, “0x01001”, “0x00101”,
“0x00011” or “0x00001” in the lower five bits will have no effect.