When addressing I/O Registers as data space using LD
and ST instructions, the provided offset must be used. When using the I/O specific
commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset
within 0x00 - 0x3F.
Analog Comparator
Disable
When this bit is
written logic one, the power to the Analog Comparator is switched off. This bit can
be set at any time to turn off the Analog Comparator. This will reduce power
consumption in Active and Idle mode. When changing the ACD bit, the Analog
Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an
interrupt can occur when the bit is changed.
Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces
the positive input to the Analog Comparator. When this bit is cleared, AIN0 is
applied to the positive input of the Analog Comparator. When the bandgap reference
is used as input to the Analog Comparator, it will take a certain time for the
voltage to stabilize. If not stabilized, the first conversion may give a wrong
value.
Analog Comparator Output
The output of the Analog Comparator is synchronized and then
directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock
cycles.
Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers
the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt
routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is
cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ACI is cleared by writing a logic one to the
flag.
Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status
Register is set, the Analog Comparator interrupt is activated. When written logic
zero, the interrupt is disabled.
Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function
in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is
in this case directly connected to the input capture front-end logic, making the
comparator utilize the noise canceler and edge select features of the Timer/Counter1
Input Capture interrupt. When written logic zero, no connection between the Analog
Comparator and the input capture function exists. To make the comparator trigger the
Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask
Register (TIMSK1) must be set.
Analog Comparator
Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator
interrupt.
Table 1. ACIS[1:0] Settings
ACIS1 |
ACIS0 |
Interrupt Mode |
0 |
0 |
Comparator Interrupt on Output Toggle. |
0 |
1 |
Reserved |
1 |
0 |
Comparator Interrupt on Falling Output Edge. |
1 |
1 |
Comparator Interrupt on Rising Output Edge. |
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be
disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an
interrupt can occur when the bits are changed.