SPI Control Register 0
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SPIE | SPE | DORD | MSTR | CPOL | CPHA | SPR0 [1:0] | |
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
SPI0 Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global Interrupt Enable bit in SREG is set.
SPI0 Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations.
Data0 Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
Master/Slave0 Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode.
Clock0 Polarity
Clock0 Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to Figure 1 and Figure 2 for an example. The CPHA functionality is summarized below:
| CPHA | Leading Edge | Trailing Edge |
|---|---|---|
| 0 | Sample | Setup |
| 1 | Setup | Sample |
SPI0 Clock Rate Select
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the table below.
| SPI2X | SPR0[1] | SPR0[0] | SCK Frequency |
|---|---|---|---|
| 0 | 0 | 0 | fosc/4 |
| 0 | 0 | 1 | fosc/16 |
| 0 | 1 | 0 | fosc/64 |
| 0 | 1 | 1 | fosc/128 |
| 1 | 0 | 0 | fosc/2 |
| 1 | 0 | 1 | fosc/8 |
| 1 | 1 | 0 | fosc/32 |
| 1 | 1 | 1 | fosc/64 |