The Phase Correct PWM mode (WGMn[2:0]=0x1 or WGMn[2:0]=0x5) provides a high resolution, phase correct PWM waveform generation. The Phase Correct PWM mode is based on dual-slope operation: The counter counts repeatedly from BOTTOM to TOP, and then from TOP to BOTTOM. When WGMn[2:0]=0x1 TOP is defined as 0xFF. When WGMn[2:0]=0x5, TOP is defined as OCRnA. In non-inverting Compare Output mode, the Output Compare (OCnx) bit is cleared on compare match between TCNTn and OCRnx while up-counting, and OCnx is set on the compare match while down-counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has a lower maximum operation frequency than single slope operation. Due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications.
In Phase Correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the Phase Correct PWM mode is shown below. The TCNTn value is shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn.
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value.
In Phase Correct PWM mode, the compare unit allows generation of PWM waveforms on the OCnx pin. Writing the COMnx[1:0] bits to 0x2 will produce a non-inverted PWM. An inverted PWM output can be generated by writing COMnx[1:0]=0x3: Setting the Compare Match Output A Mode bit to '1' (TCCRnA.COMnA0) allows the OCnA pin to toggle on Compare Matches if the TCCRnB.WGMn2 bit is set. This option is not available for the OCnB pin. The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OCnx Register at the compare match between OCRnx and TCNTn when the counter increments, and setting (or clearing) the OCnx Register at compare match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using Phase Correct PWM can be calculated by:
N represents the prescaler factor (1, 8, 64, 256, or 1024).
The extreme values for the OCRnA Register represent special cases when generating a PWM waveform output in the Phase Correct PWM mode: If the OCRnA register is written equal to BOTTOM, the output will be continuously low. If OCRnA is written to MAX, the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in the timing diagram above, OCnx has a transition from high to low even though there is no Compare Match. This transition serves to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match:
- OCRnx changes its value from MAX, as in the timing diagram. When the OCRnA value is MAX, the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCnx value at MAX must correspond to the result of an up-counting Compare Match.
- The timer starts up-counting from a value higher than the one in OCRnx, and for that reason misses the Compare Match and consequently, the OCnx does not undergo the change that would have happened on the way up.