Interrupt Controlled Transfer

In interrupt controlled transfer, the USART generates an interrupt when the USART has finished transmitting or receiving a byte. Thus the CPU can perform other functions while the USART module transmit or receive a byte. Interrupts corresponding to receive and transmit functionality of the USART module should be enabled for interrupt controlled transfers. In addition to this the Global Interrupt Enable bit in SREG must be set for the interrupts to be enabled.