Bandwidth and Input Impedance

When using single-ended mode, the ADC bandwidth is limited by the ADC clock speed. Since one conversion takes 13 ADC clock cycles, a maximum ADC clock of 1MHz means approximately 77ksps (kilo samples per second). This limits the bandwidth in single-ended mode to 38.5kHz, according to the Nyquist sampling theorem.

When using differential mode, the bandwidth is limited to 4kHz by the differential amplifier. Input frequency components above 4kHz should be removed by an external analog filter, to avoid non-linearity’s.

The input impedance to VCC and GND is typically 100MΩ. Together with the output impedance of the signal source, this creates a voltage divider. The signal source should therefore have sufficiently low output impedance to get correct conversion results.