Contents

Introduction PIC16F181 Family Summary Core Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features Block Diagram 4. Packages 5. Pin Diagrams 6. Pin Allocation Tables 7. Guidelines for Getting Started with PIC16F181 Microcontrollers 7.1. Basic Connection Requirements 7.2. Power Supply Pins 7.2.1. Decoupling Capacitors 7.2.2. Tank Capacitors 7.3. Master Clear (MCLR) Pin 7.4. In-Circuit Serial Programming (ICSP) Pins 7.5. Unused I/Os 8. Register and Bit Naming Conventions 8.1. Register Names 8.2. Bit Names 8.2.1. Short Bit Names 8.2.2. Long Bit Names 8.2.3. Bit Fields 8.3. Register and Bit Naming Exceptions 8.3.1. Status, Interrupt and Mirror Bits 9. Register Legend 10. Enhanced Mid-Range CPU 10.1. Automatic Interrupt Context Saving 10.2. 16-Level Stack with Overflow and Underflow 10.3. File Select Registers 10.4. Instruction Set 11. Device Configuration 11.1. Configuration Words 11.2. Code Protection 11.3. Write Protection 11.4. User ID 11.5. Device ID and Revision ID 11.6. Register Definitions: Configuration Settings 11.6.1. CONFIG1 11.6.2. CONFIG2 11.6.3. CONFIG3 11.6.4. CONFIG4 11.6.5. CONFIG5 11.7. Register Definitions: Device ID and Revision ID 11.7.1. Device ID 11.7.2. Revision ID 12. Memory Organization 12.1. Program Memory Organization 12.1.1. Reading Program Memory as Data 12.1.1.1. RETLW Instruction 12.1.1.2. Indirect Read with FSR 12.1.2. Memory Access Partition (MAP) 12.1.2.1. Application Block 12.1.2.2. Boot Block 12.1.2.3. Storage Area Flash 12.1.2.4. Memory Write Protection 12.1.2.5. Memory Violation 12.1.3. Device Information Area (DIA) 12.1.3.1. Microchip Unique Identifier (MUI) 12.1.3.2. External Unique Identifier (EUI) 12.1.3.3. Standard Parameters for the Temperature Sensor 12.1.3.4. Fixed Voltage Reference Data 12.1.4. Device Configuration Information (DCI) 12.1.4.1. DIA and DCI Access 12.2. Data Memory Organization 12.2.1. Bank Selection 12.2.2. Core Registers 12.2.3. Special Function Register 12.2.4. General Purpose RAM 12.2.5. Common RAM 12.2.6. Device Memory Maps 12.3. STATUS Register 12.4. PCL and PCLATH 12.4.1. Modifying PCL 12.4.2. Computed GOTO 12.4.3. Computed Function Calls 12.4.4. Branching 12.5. Stack 12.5.1. Accessing the Stack 12.5.2. Overflow/Underflow Reset 12.6. Indirect Addressing 12.6.1. Traditional/Banked Data Memory 12.6.2. Linear Data Memory 12.6.3. Program Flash Memory 12.6.4. Data EEPROM Memory 12.7. Register Definitions: Memory Organization 12.7.1. INDF0 12.7.2. INDF1 12.7.3. PCL 12.7.4. STATUS 12.7.5. FSR0 12.7.6. FSR1 12.7.7. BSR 12.7.8. WREG 12.7.9. PCLATH 12.8. Register Summary - Memory Organization 13. Resets 13.1. Power-on Reset (POR) 13.1.1. Programming Mode Exit 13.2. Brown-out Reset (BOR) 13.2.1. BOR Is Always On 13.2.2. BOR Is Off in Sleep 13.2.3. BOR Controlled by Software 13.2.4. BOR Is Always Off 13.3. MCLR Reset 13.3.1. MCLR Enabled 13.3.2. MCLR Disabled 13.4. Watchdog Timer (WDT) Reset 13.5. RESET Instruction 13.6. Stack Overflow/Underflow Reset 13.7. Power-Up Timer (PWRT) 13.8. Start-Up Sequence 13.9. Memory Execution Violation 13.10. Determining the Cause of a Reset 13.11. Power Control (PCONx) Register 13.12. Register Definitions: Power Control 13.12.1. BORCON 13.12.2. PCON0 13.12.3. PCON1 13.13. Register Summary - Power Control 14. OSC - Oscillator Module (With Fail-Safe Clock Monitor) 14.1. Clock Source Types 14.1.1. External Clock Sources 14.1.1.1. EC Mode 14.1.1.2. LP, XT, HS Modes 14.1.1.3. Oscillator Start-Up Timer (OST) 14.1.1.4. 4x PLL 14.1.1.5. Secondary Oscillator 14.1.1.5.1. SOSC Start-Up Timing 14.1.2. Internal Clock Sources 14.1.2.1. HFINTOSC 14.1.2.1.1. HFINTOSC Frequency Tuning 14.1.2.2. MFINTOSC 14.1.2.3. SFINTOSC 14.1.2.4. LFINTOSC 14.1.2.5. ADCRC 14.1.3. Oscillator Status and Manual Enable 14.2. Clock Switching 14.2.1. NOSC and NDIV Bits 14.2.2. COSC and CDIV Bits 14.2.3. CSWHOLD 14.2.4. PLL Input Switch 14.2.5. Clock Switch and Sleep 14.3. Fail-Safe Clock Monitor (FSCM) 14.3.1. Fail-Safe Detection 14.3.2. Fail-Safe Operation 14.3.3. Fail-Safe Condition Clearing 14.3.4. Reset or Wake-Up from Sleep 14.4. Active Clock Tuning (ACT) 14.4.1. ACT Lock Status 14.4.2. ACT Out-of-Range Status 14.4.3. ACT Update Disable 14.4.4. ACT Interrupts 14.5. Register Definitions: Oscillator Module 14.5.1. ACTCON 14.5.2. OSCCON1 14.5.3. OSCCON2 14.5.4. OSCCON3 14.5.5. OSCTUNE 14.5.6. OSCFRQ 14.5.7. OSCSTAT 14.5.8. OSCEN 14.6. Register Summary - Oscillator Module 15. INT - Interrupts 15.1. Overview 15.2. INTCON Register 15.3. PIE Registers 15.4. PIR Registers 15.5. Operation 15.6. Interrupt Latency 15.7. Interrupts During Sleep 15.8. INT Pin 15.9. Automatic Context Saving 15.10. Register Definitions: Interrupt Control 15.10.1. INTCON 15.10.2. PIE0 15.10.3. PIE1 15.10.4. PIE2 15.10.5. PIE3 15.10.6. PIE4 15.10.7. PIE5 15.10.8. PIE6 15.10.9. PIR0 15.10.10. PIR1 15.10.11. PIR2 15.10.12. PIR3 15.10.13. PIR4 15.10.14. PIR5 15.10.15. PIR6 15.11. Register Summary - Interrupt Control 16. Power-Saving Modes 16.1. Doze Mode 16.1.1. Doze Operation 16.1.2. Interrupts During Doze 16.2. Sleep Mode 16.2.1. Wake-Up from Sleep 16.2.2. Wake-Up Using Interrupts 16.3. Idle Mode 16.3.1. Idle and Interrupts 16.3.2. Idle and WWDT 16.4. Peripheral Operation in Power-Saving Modes 16.5. Register Definitions: Power-Savings Control 16.5.1. CPUDOZE 16.6. Register Summary - Power-Savings Control 17. WWDT - Windowed Watchdog Timer 17.1. Independent Clock Source 17.2. WWDT Operating Modes 17.2.1. WWDT Is Always On 17.2.2. WWDT Is Off in Sleep 17.2.3. WWDT Controlled by Software 17.3. Time-Out Period 17.4. Watchdog Window 17.5. Clearing the Watchdog Timer 17.5.1. CLRWDT Considerations (Windowed Mode) 17.6. Operation During Sleep 17.7. Register Definitions: Windowed Watchdog Timer Control 17.7.1. WDTCON0 17.7.2. WDTCON1 17.7.3. WDTPSH 17.7.4. WDTPSL 17.7.5. WDTTMR 17.8. Register Summary - WDT Control 18. NVM - Nonvolatile Memory Control 18.1. Program Flash Memory (PFM) 18.1.1. FSR and INDF Access 18.1.1.1. FSR Read 18.1.1.2. FSR Write 18.1.2. NVMREG Access 18.1.2.1. NVMREG Read Operation 18.1.2.2. NVM Unlock Sequence 18.1.2.3. NVMREG Erase of Program Memory 18.1.2.4. NVMREG Write to Program Memory 18.1.2.5. Modifying Flash Program Memory 18.1.2.6. NVMREG Access to DIA, DCI, User ID, Device ID, Revision ID, and Configuration Words 18.1.2.7. Write Verify 18.1.2.8. WRERR Bit 18.2. Data Flash Memory (DFM) 18.2.1. FSR and INDF Access 18.2.1.1. FSR DFM Read 18.2.1.2. FSR DFM Write 18.2.2. NVMREG Access 18.2.2.1. NVMREG Read Operation 18.2.2.2. NVM Unlock Sequence 18.2.2.3. NVMREG Erase of DFM 18.2.2.4. NVMREG Write to DFM 18.2.2.5. WRERR Bit 18.3. Register Definitions: Nonvolatile Memory Control 18.3.1. NVMADR 18.3.2. NVMDAT 18.3.3. NVMCON1 18.3.4. NVMCON2 18.4. Register Summary - NVM Control 19. I/O Ports 19.1. Overview 19.2. PORTx - Data Register 19.3. LATx - Output Latch 19.4. TRISx - Direction Control 19.5. ANSELx - Analog Control 19.6. WPUx - Weak Pull-Up Control 19.7. INLVLx - Input Threshold Control 19.8. SLRCONx - Slew Rate Control 19.9. ODCONx - Open-Drain Control 19.10. Edge Selectable Interrupt-on-Change 19.11. I2C Pad Control 19.12. I/O Priorities 19.13. MCLR/VPP/RA3 Pin 19.14. Register Definitions: Port Control 19.14.1. PORTx 19.14.2. LATx 19.14.3. TRISx 19.14.4. ANSELx 19.14.5. WPUx 19.14.6. INLVLx 19.14.7. SLRCONx 19.14.8. ODCONx 19.14.9. RxyI2C 19.15. Register Summary - IO Ports 20. IOC - Interrupt-on-Change 20.1. Overview 20.2. Enabling the Module 20.3. Individual Pin Configuration 20.4. Interrupt Flags 20.5. Clearing Interrupt Flags 20.6. Operation in Sleep 20.7. Register Definitions: Interrupt-on-Change Control 20.7.1. IOCxF 20.7.2. IOCxN 20.7.3. IOCxP 20.8. Register Summary - Interrupt-on-Change 21. PPS - Peripheral Pin Select Module 21.1. Overview 21.2. PPS Inputs 21.3. PPS Outputs 21.4. Bidirectional Pins 21.5. PPS Lock 21.5.1. PPS One-Way Lock 21.6. Operation During Sleep 21.7. Effects of a Reset 21.8. Register Definitions: Peripheral Pin Select (PPS) 21.8.1. xxxPPS 21.8.2. RxyPPS 21.8.3. PPSLOCK 21.9. Register Summary - Peripheral Pin Select Module 22. CRC - Cyclic Redundancy Check Module with Memory Scanner 22.1. Module Overview 22.2. Polynomial Implementation 22.3. Data Sources 22.3.1. CRC from User Data 22.3.2. CRC from Flash 22.4. CRC Check Value 22.5. CRC Interrupt 22.6. Configuring the CRC Module 22.6.1. Register Overlay 22.7. Scanner Module Overview 22.8. Scanning Modes 22.8.1. Concurrent Mode 22.8.2. Burst Mode 22.8.3. Peek Mode 22.8.4. Triggered Mode 22.9. Configuring the Scanner 22.10. Scanner Interrupts 22.10.1. Operation During Interrupts 22.11. WWDT Interaction 22.12. Operation During Sleep 22.13. Peripheral Module Disable 22.14. Register Definitions: CRC and Scanner Control 22.14.1. CRCCON0 22.14.2. CRCCON1 22.14.3. CRCCON2 22.14.4. CRCDATA 22.14.5. CRCOUT 22.14.6. CRCSHIFT 22.14.7. CRCXOR 22.14.8. SCANCON0 22.14.9. SCANLADR 22.14.10. SCANHADR 22.14.11. SCANTRIG 22.15. Register Summary - CRC 23. PMD - Peripheral Module Disable 23.1. Overview 23.2. Disabling a Module 23.3. Enabling a Module 23.4. Register Definitions: Peripheral Module Disable 23.4.1. PMD0 23.4.2. PMD1 23.4.3. PMD2 23.4.4. PMD3 23.4.5. PMD4 23.5. Register Summary - PMD 24. CLKREF - Reference Clock Output Module 24.1. Clock Source 24.1.1. Clock Synchronization 24.2. Programmable Clock Divider 24.3. Selectable Duty Cycle 24.4. Operation in Sleep Mode 24.5. Register Definitions: Reference Clock 24.5.1. CLKRCON 24.5.2. CLKRCLK 24.6. Register Summary - Reference CLK 25. TMR0 - Timer0 Module 25.1. Timer0 Operation 25.1.1. 8-Bit Mode 25.1.2. 16-Bit Mode 25.2. Clock Selection 25.2.1. Synchronous Mode 25.2.2. Asynchronous Mode 25.2.3. Programmable Prescaler 25.2.4. Programmable Postscaler 25.3. Timer0 Output and Interrupt 25.3.1. Timer0 Output 25.3.2. Timer0 Interrupt 25.3.3. Timer0 Example 25.4. Operation During Sleep 25.5. Register Definitions: Timer0 Control 25.5.1. T0CON0 25.5.2. T0CON1 25.5.3. TMR0H 25.5.4. TMR0L 25.6. Register Summary - Timer0 26. TMR1 - Timer1 Module with Gate Control 26.1. Timer1 Operation 26.2. Clock Source Selection 26.2.1. Internal Clock Source 26.2.2. External Clock Source 26.3. Timer1 Prescaler 26.4. Secondary Oscillator 26.5. Timer1 Operation in Asynchronous Counter Mode 26.5.1. Reading and Writing TMRx in Asynchronous Counter Mode 26.6. Timer1 16-Bit Read/Write Mode 26.7. Timer1 Gate 26.7.1. Timer1 Gate Enable 26.7.2. Timer1 Gate Source Selection 26.7.3. Timer1 Gate Toggle Mode 26.7.4. Timer1 Gate Single Pulse Mode 26.7.5. Timer1 Gate Value Status 26.7.6. Timer1 Gate Event Interrupt 26.8. Timer1 Interrupt 26.9. Timer1 Operation During Sleep 26.10. CCP Capture/Compare Time Base 26.11. CCP Special Event Trigger 26.12. Peripheral Module Disable 26.13. Register Definitions: Timer1 Control 26.13.1. TxCON 26.13.2. TxGCON 26.13.3. TxCLK 26.13.4. TxGATE 26.13.5. TMRx 26.14. Register Summary - Timer1 27. TMR2 - Timer2 Module 27.1. Timer2 Operation 27.1.1. Free-Running Period Mode 27.1.2. One Shot Mode 27.1.3. Monostable Mode 27.2. Timer2 Output 27.3. External Reset Sources 27.4. Timer2 Interrupt 27.5. PSYNC Bit 27.6. CSYNC Bit 27.7. Operating Modes 27.8. Operation Examples 27.8.1. Software Gate Mode 27.8.2. Hardware Gate Mode 27.8.3. Edge Triggered Hardware Limit Mode 27.8.4. Level Triggered Hardware Limit Mode 27.8.5. Software Start One Shot Mode 27.8.6. Edge Triggered One Shot Mode 27.8.7. Edge Triggered Hardware Limit One Shot Mode 27.8.8. Level Reset, Edge Triggered Hardware Limit One Shot Modes 27.8.9. Edge Triggered Monostable Modes 27.8.10. Level Triggered Hardware Limit One Shot Modes 27.9. Timer2 Operation During Sleep 27.10. Register Definitions: Timer2 Control 27.10.1. TxTMR 27.10.2. TxPR 27.10.3. TxCON 27.10.4. TxHLT 27.10.5. TxCLKCON 27.10.6. TxRST 27.11. Register Summary - Timer2 28. NCO - Numerically Controlled Oscillator Module 28.1. NCO Operation 28.1.1. NCO Clock Sources 28.1.2. Accumulator 28.1.3. Adder 28.1.4. Increment Registers 28.2. Fixed Duty Cycle Mode 28.3. Pulse Frequency Mode 28.4. Output Polarity Control 28.5. Interrupts 28.6. Effects of a Reset 28.7. Operation in Sleep 28.8. Register Definitions: NCO 28.8.1. NCOxCON 28.8.2. NCOxCLK 28.8.3. NCOxACC 28.8.4. NCOxINC 28.9. Register Summary - NCO 29. CWG - Complementary Waveform Generator Module 29.1. Fundamental Operation 29.2. Operating Modes 29.2.1. Half Bridge Mode 29.2.2. Push-Pull Mode 29.2.3. Full Bridge Mode 29.2.3.1. Direction Change in Full Bridge Mode 29.2.3.2. Dead-Band Delay in Full Bridge Mode 29.2.4. Steering Modes 29.2.4.1. Synchronous Steering Mode 29.2.4.2. Asynchronous Steering Mode 29.2.4.3. Start-Up Considerations 29.3. Clock Source 29.4. Selectable Input Sources 29.5. Output Control 29.5.1. CWG Output 29.5.2. Polarity Control 29.6. Dead-Band Control 29.6.1. Dead-Band Functionality in Half Bridge Mode 29.6.2. Dead-Band Functionality in Full Bridge Mode 29.7. Rising Edge and Reverse Dead Band 29.8. Falling Edge and Forward Dead Band 29.9. Dead-Band Jitter 29.10. Auto-Shutdown 29.10.1. Shutdown 29.10.2. Software Generated Shutdown 29.10.3. External Input Source 29.10.4. Pin Override Levels 29.10.5. Auto-Shutdown Interrupts 29.11. Auto-Shutdown Restart 29.11.1. Software-Controlled Restart 29.11.2. Auto-Restart 29.12. Operation During Sleep 29.13. Configuring the CWG 29.14. Register Definitions: CWG Control 29.14.1. CWGxCON0 29.14.2. CWGxCON1 29.14.3. CWGxCLK 29.14.4. CWGxISM 29.14.5. CWGxSTR 29.14.6. CWGxAS0 29.14.7. CWGxAS1 29.14.8. CWGxDBR 29.14.9. CWGxDBF 29.15. Register Summary - CWG 30. CCP - Capture/Compare/PWM Module 30.1. CCP Module Configuration 30.1.1. CCP Modules and Timer Resources 30.1.2. Open-Drain Output Option 30.2. Capture Mode 30.2.1. Capture Sources 30.2.2. Timer1 Mode for Capture 30.2.3. Software Interrupt Mode 30.2.4. CCP Prescaler 30.2.5. Capture During Sleep 30.3. Compare Mode 30.3.1. CCPx Pin Configuration 30.3.2. Timer1 Mode for Compare 30.3.3. Compare During Sleep 30.4. PWM Overview 30.4.1. Standard PWM Operation 30.4.2. Setup for PWM Operation 30.4.3. Timer2 Timer Resource 30.4.4. PWM Period 30.4.5. PWM Duty Cycle 30.4.6. PWM Resolution 30.4.7. Operation in Sleep Mode 30.4.8. Changes in System Clock Frequency 30.4.9. Effects of Reset 30.5. Register Definitions: CCP Control 30.5.1. CCPxCON 30.5.2. CCPxCAP 30.5.3. CCPRx 30.6. Register Summary - CCP Control 31. Capture, Compare, and PWM Timers Selection 31.1. Register Definitions: Capture, Compare, and PWM Timers Selection 31.1.1. CCPTMRS0 31.2. Register Summary - Capture, Compare, and PWM Timers Selection 32. PWM - Pulse-Width Modulator with Compare 32.1. Output Slices 32.1.1. Output Polarity 32.1.2. Operating Modes 32.1.2.1. Left Aligned Mode 32.1.2.2. Right Aligned Mode 32.1.2.3. Center-Aligned Mode 32.1.2.4. Variable Alignment Mode 32.1.2.5. Compare Modes 32.1.2.5.1. Pulsed Compare Mode 32.1.2.5.2. Toggled Compare 32.1.3. Push-Pull Mode 32.2. Period Timer 32.3. Clock Sources 32.3.1. Clock Prescaler 32.4. External Period Resets 32.5. Buffered Period and Parameter Registers 32.6. Synchronizing Multiple PWMs 32.7. Interrupts 32.7.1. Period Interrupt 32.7.1.1. Period Interrupt Postscaler 32.7.2. Parameter Interrupts 32.8. Operation During Sleep 32.9. Register Definitions: PWM Control 32.9.1. PWMxERS 32.9.2. PWMxCLK 32.9.3. PWMxLDS 32.9.4. PWMxPR 32.9.5. PWMxCPRE 32.9.6. PWMxPIPOS 32.9.7. PWMxGIR 32.9.8. PWMxGIE 32.9.9. PWMxCON 32.9.10. PWMxSaCFG 32.9.11. PWMxSaP1 32.9.12. PWMxSaP2 32.9.16. PWMLOAD 32.9.17. PWMEN 32.10. Register Summary - PWM 33. CLC - Configurable Logic Cell 33.1. CLC Setup 33.1.1. Data Selection 33.1.2. Data Gating 33.1.3. Logic Function 33.1.4. Output Polarity 33.2. CLC Interrupts 33.3. Effects of a Reset 33.4. Output Mirror Copies 33.5. Operation During Sleep 33.6. CLC Setup Steps 33.7. Register Overlay 33.8. Register Definitions: Configurable Logic Cell 33.8.1. CLCSELECT 33.8.2. CLCnCON 33.8.3. CLCnPOL 33.8.4. CLCnSEL0 33.8.5. CLCnSEL1 33.8.6. CLCnSEL2 33.8.7. CLCnSEL3 33.8.8. CLCnGLS0 33.8.9. CLCnGLS1 33.8.10. CLCnGLS2 33.8.11. CLCnGLS3 33.8.12. CLCDATA 33.9. Register Summary - CLC Control 34. MSSP - Host Synchronous Serial Port Module 34.1. SPI Mode Overview 34.1.1. SPI Mode Registers 34.1.2. SPI Mode Operation 34.1.2.1. SPI Host Mode 34.1.2.2. SPI Client Mode 34.1.2.3. Daisy-Chain Configuration 34.1.2.4. Client Select Synchronization 34.1.2.5. SPI Operation in Sleep Mode 34.2. I2C Mode Overview 34.2.1. I2C Mode Registers 34.2.2. I2C Mode Operation 34.2.2.1. Definition of I2C Terminology 34.2.2.2. Byte Format 34.2.2.3. SDA and SCL Pins 34.2.2.4. SDA Hold Time 34.2.2.5. Clock Stretching 34.2.2.6. Arbitration 34.2.2.7. Start Condition 34.2.2.8. Stop Condition 34.2.2.9. Start/Stop Condition Interrupt Masking 34.2.2.10. Restart Condition 34.2.2.11. Acknowledge Sequence 34.2.3. I2C Client Mode Operation 34.2.3.1. Client Mode Addresses 34.2.3.1.1. I2C Client 7-Bit Addressing Mode 34.2.3.1.2. I2C Client 10-Bit Addressing Mode 34.2.3.2. Clock Stretching 34.2.3.2.1. Normal Clock Stretching 34.2.3.2.2. 10-Bit Addressing Mode 34.2.3.2.3. Byte NACKing 34.2.3.3. Clock Synchronization and the CKP Bit 34.2.3.4. General Call Address Support 34.2.3.5. SSP Mask Register 34.2.3.6. Client Reception 34.2.3.6.1. 7-Bit Addressing Reception 34.2.3.6.2. 7-Bit Reception with AHEN and DHEN 34.2.3.6.3. Client Mode 10-Bit Address Reception 34.2.3.6.4. 10-Bit Addressing with Address or Data Hold 34.2.3.7. Client Transmission 34.2.3.7.1. Client Mode Bus Collision 34.2.3.7.2. 7-Bit Transmission 34.2.3.7.3. 7-Bit Transmission with Address Hold Enabled 34.2.4. I2C Host Mode 34.2.4.1. I2C Host Mode Operation 34.2.4.1.1. Clock Arbitration 34.2.4.1.2. WCOL Status Flag 34.2.4.1.3. I2C Host Mode Start Condition Timing 34.2.4.1.4. I2C Host Mode Repeated Start Condition Timing 34.2.4.1.5. Acknowledge Sequence Timing 34.2.4.1.5.1. Acknowledge Write Collision 34.2.4.1.6. Stop Condition Timing 34.2.4.1.6.1. Write Collision on Stop 34.2.4.1.7. Sleep Operation 34.2.4.1.8. Effects of a Reset 34.2.4.2. I2C Host Mode Transmission 34.2.4.2.1. BF Status Flag 34.2.4.2.2. WCOL Status Flag 34.2.4.2.3. ACKSTAT Status Flag 34.2.4.2.4. Typical Transmit Sequence 34.2.4.3. I2C Host Mode Reception 34.2.4.3.1. BF Status Flag 34.2.4.3.2. SSPOV Status Flag 34.2.4.3.3. WCOL Status Flag 34.2.4.3.4. Typical Receive Sequence 34.2.5. Multi-Host Mode 34.2.5.1. Multi-Host Communication, Bus Collision and Bus Arbitration 34.2.5.1.1. Bus Collision During a Start Condition 34.2.5.1.2. Bus Collision During a Repeated Start Condition 34.2.5.1.3. Bus Collision During a Stop Condition 34.3. Baud Rate Generator 34.4. Register Definitions: MSSP Control 34.4.1. SSPxBUF 34.4.2. SSPxADD 34.4.3. SSPxMSK 34.4.4. SSPxSTAT 34.4.5. SSPxCON1 34.4.6. SSPxCON2 34.4.7. SSPxCON3 34.5. Register Summary - MSSP Control 35. EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter 35.1. EUSART Asynchronous Mode 35.1.1. EUSART Asynchronous Transmitter 35.1.1.1. Enabling the Transmitter 35.1.1.2. Transmitting Data 35.1.1.3. Transmit Data Polarity 35.1.1.4. Transmit Interrupt Flag 35.1.1.5. TSR Status 35.1.1.6. Transmitting 9-Bit Characters 35.1.1.7. Asynchronous Transmission Setup 35.1.2. EUSART Asynchronous Receiver 35.1.2.1. Enabling the Receiver 35.1.2.2. Receiving Data 35.1.2.3. Receive Interrupts 35.1.2.4. Receive Framing Error 35.1.2.5. Receive Overrun Error 35.1.2.6. Receiving 9-Bit Characters 35.1.2.7. Address Detection 35.1.2.8. Asynchronous Reception Setup 35.1.2.9. 9-Bit Address Detection Mode Setup 35.2. Clock Accuracy with Asynchronous Operation 35.3. EUSART Baud Rate Generator (BRG) 35.3.1. Auto-Baud Detect 35.3.2. Auto-Baud Overflow 35.3.3. Auto-Wake-Up on Break 35.3.3.1. Special Considerations 35.3.4. Break Character Sequence 35.3.4.1. Break and Sync Transmit Sequence 35.3.5. Receiving a Break Character 35.4. EUSART Synchronous Mode 35.4.1. Synchronous Host Mode 35.4.1.1. Host Clock 35.4.1.2. Clock Polarity 35.4.1.3. Synchronous Host Transmission 35.4.1.4. Synchronous Host Transmission Setup 35.4.1.5. Synchronous Host Reception 35.4.1.6. Client Clock 35.4.1.7. Receive Overrun Error 35.4.1.8. Receiving 9-Bit Characters 35.4.1.9. Synchronous Host Reception Setup 35.4.2. Synchronous Client Mode 35.4.2.1. EUSART Synchronous Client Transmit 35.4.2.2. Synchronous Client Transmission Setup 35.4.2.3. EUSART Synchronous Client Reception 35.4.2.4. Synchronous Client Reception Setup 35.5. EUSART Operation During Sleep 35.5.1. Synchronous Receive During Sleep 35.5.2. Synchronous Transmit During Sleep 35.6. Register Definitions: EUSART Control 35.6.1. TXxSTA 35.6.2. RCxSTA 35.6.3. BAUDxCON 35.6.4. RCxREG 35.6.5. TXxREG 35.6.6. SPxBRG 35.7. Register Summary - EUSART 36. ADC - Analog-to-Digital Converter with Computation Module 36.1. ADC Configuration 36.1.1. ADC Input Configuration 36.1.2. Port Configuration 36.1.3. Channel Selection 36.1.3.1. Channel Grouping 36.1.4. ADC Voltage Reference 36.1.5. Conversion Clock 36.1.6. Interrupts 36.1.7. Result Formatting 36.1.7.1. Sign/Magnitude and Two’s Complement Result 36.2. ADC Operation 36.2.1. Starting a Conversion 36.2.2. Completion of a Conversion 36.2.3. ADC Operation During Sleep 36.2.4. External Trigger During Sleep 36.2.5. Auto-Conversion Trigger 36.2.6. ADC Conversion Procedure (Basic Mode) 36.3. ADC Acquisition Requirements 36.4. Computation Operation 36.4.1. Digital Filter/Average 36.4.2. Basic Mode 36.4.3. Accumulate Mode 36.4.4. Average Mode 36.4.5. Burst Average Mode 36.4.6. Low-Pass Filter Mode 36.4.7. Threshold Comparison 36.4.8. Repetition and Sampling Options 36.4.8.1. Continuous Sampling Mode 36.4.8.2. Double Sample Conversion 36.4.9. Capacitive Voltage Divider (CVD) Features 36.4.9.1. CVD Operation 36.4.9.2. Precharge Control 36.4.9.3. Acquisition Control for CVD (ADPRE > 0) 36.4.9.4. Guard Ring Outputs 36.4.9.5. Additional Sample-and-Hold Capacitance 36.5. Register Definitions: ADC Control 36.5.1. ADCON0 36.5.2. ADCON1 36.5.3. ADCON2 36.5.4. ADCON3 36.5.5. ADSTAT 36.5.6. ADCLK 36.5.7. ADREF 36.5.8. ADPCH 36.5.9. ADNCH 36.5.10. ADPRE 36.5.11. ADACQ 36.5.12. ADCAP 36.5.13. ADRPT 36.5.14. ADCNT 36.5.15. ADFLTR 36.5.16. ADRES 36.5.17. ADPREV 36.5.18. ADACC 36.5.19. ADSTPT 36.5.20. ADERR 36.5.21. ADLTH 36.5.22. ADUTH 36.5.23. ADACT 36.5.24. ADCGxA 36.5.25. ADCGxB 36.5.26. ADCGxC 36.6. Register Summary - ADC 37. DAC - Digital-to-Analog Converter Module 37.1. Output Voltage Selection 37.2. Ratiometric Output Level 37.3. Buffered DAC Output Range Selection 37.4. Operation During Sleep 37.5. Effects of a Reset 37.6. Register Definitions: DAC Control 37.6.1. DACxCON 37.6.2. DACxDATL 37.7. Register Summary - DAC 38. CMP - Comparator Module 38.1. Comparator Overview 38.2. Comparator Control 38.2.1. Comparator Enable 38.2.2. Comparator Output 38.2.3. Comparator Output Polarity 38.3. Comparator Output Synchronization 38.4. Comparator Hysteresis 38.5. Comparator Interrupt 38.6. Comparator Positive Input Selection 38.7. Comparator Negative Input Selection 38.8. Comparator Response Time 38.9. Analog Input Connection Considerations 38.10. Operation in Sleep Mode 38.11. ADC Auto-Trigger Source 38.12. Register Definitions: Comparator Control 38.12.1. CMxCON0 38.12.2. CMxCON1 38.12.3. CMxNCH 38.12.4. CMxPCH 38.12.5. CMOUT 38.13. Register Summary - Comparator 39. FVR - Fixed Voltage Reference 39.1. Independent Gain Amplifiers 39.2. FVR Stabilization Period 39.3. Register Definitions: FVR 39.3.1. FVRCON 39.4. Register Summary - FVR 40. Temperature Indicator Module 40.1. Module Operation 40.1.1. Temperature Indicator Range 40.1.2. Minimum Operating VDD 40.2. Temperature Calculation 40.3. ADC Acquisition Time 40.4. Register Definitions: Temperature Indicator 40.4.1. FVRCON 40.5. Register Summary - Temperature Indicator 41. ZCD - Zero-Cross Detection Module 41.1. External Resistor Selection 41.2. ZCD Logic Output 41.3. ZCD Logic Polarity 41.4. ZCD Interrupts 41.5. Correction for ZCPINV Offset 41.5.1. Correction by AC Coupling 41.5.2. Correction by Offset Current 41.6. Handling VPEAK Variations 41.7. Operation During Sleep 41.8. Effects of a Reset 41.9. Disabling the ZCD Module 41.10. Register Definitions: ZCD Control 41.10.1. ZCDCON 41.11. Register Summary - ZCD 42. Charge Pump 42.1. Manually Enabled 42.2. Automatically Enabled 42.3. Disabled 42.4. Charge Pump Oscillator 42.5. Charge Pump Threshold 42.6. Charge Pump Ready 42.7. Register Definitions: Charge Pump 42.7.1. CPCON 42.8. Register Summary - Charge Pump 43. Instruction Set Summary 43.1. Read-Modify-Write Operations 43.2. Standard Instruction Set 43.2.1. Standard Instruction Set 44. ICSP™ - In-Circuit Serial Programming™ 44.1. High-Voltage Programming Entry Mode 44.2. Low-Voltage Programming Entry Mode 44.3. Common Programming Interfaces 45. Register Summary 46. Electrical Specifications 46.1. Absolute Maximum Ratings(†) 46.2. Standard Operating Conditions 46.3. DC Characteristics 46.3.1. Supply Voltage 46.3.2. Supply Current (IDD)(1,2) 46.3.3. Power-Down Current (IPD)(1,2,3) 46.3.4. I/O Ports 46.3.5. Memory Programming Specifications 46.3.6. Thermal Characteristics 46.4. AC Characteristics 46.4.1. External Clock/Oscillator Timing Requirements 46.4.2. Internal Oscillator Parameters(1) 46.4.3. I/O and CLKOUT Timing Specifications 46.4.4. Reset, WDT, Power-up Timer, and Brown-Out Reset Specifications 46.4.5. Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2) 46.4.6. Analog-to-Digital Converter (ADC) Conversion Timing Specifications 46.4.7. 8-Bit DAC Specifications 46.4.8. Comparator Specifications 46.4.9. Zero-Cross Detect (ZCD) Specifications 46.4.10. Fixed Voltage Reference (FVR) Specifications 46.4.11. Temperature Indicator Requirements 46.4.12. Timer0 and Timer1 External Clock Requirements 46.4.13. Capture/Compare/PWM Requirements (CCP) 46.4.14. EUSART Synchronous Transmission Requirements 46.4.15. EUSART Synchronous Receive Requirements 46.4.16. SPI Mode Requirements 46.4.17. I2C Bus Start/Stop Bits Requirements 46.4.18. I2C Bus Data Requirements 46.4.19. Configurable Logic Cell (CLC) Characteristics 47. DC and AC Characteristics Graphs and Tables 48. Packaging Information 48.1. Package Details 49. Appendix A: Revision History The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service