ADC Conversion

When using the ADCRC as the clock source for ADCC, there is a delay of one instruction cycle between the user setting the ADGO bit and being able to read it set. This can lead to a false conversion complete scenario (i.e., ADGO being cleared), depending if the user code has a bit clear test BTFSC instruction on the ADGO bit, immediately after setting the ADGO bit. See code example below.

CopyBSF ADCON0, ADGO                    ;    Start conversion
BTSFC ADCON0, ADGO                  ;    Is conversion done?
GOTO $-1                            ;    No, test again

Work around

Add a NOP instruction after setting the ADGO bit and before testing the bit for completion of conversion. See code example below.

CopyBSF ADCON0, ADGO                    ;    Start conversion
NOP
BTSFC ADCON0, ADGO                  ;    Is conversion done?
GOTO $-1                            ;    No, test again

Affected Silicon Revisions