Master Mode

The LIN Master mode is configured using the following settings:

A master process will begin upon writing the PID to the lower six bits of the UxP1L register (The 2 parity bits of the PID are automatically calculated by the UART module). Doing this will automatically clear the UxTXCHK and UxRXCHK registers and have the UART module generate the LIN header (Break, Break Delimiter, Sync byte, and PID) and send them onto the bus. The PID is also received by the UART module and is stored in the receive FIFO of the UART. At this point, the LIN Master mode transitions into its slave process.

To send or receive data, software must read the PID and determine how many bytes are to be sent or received based on predetermined settings for each PID. Then, either program the UxP2H/L register pair with the number of bytes to transmit, or the UxP3H/L register with the number of bytes to receive. For transmission, the bytes must be written to the transmit FIFO of the UART, while reception will store the bytes read to the receive FIFO. In addition, the PID will determine which checksum should be used for the data that is sent or received, and the C0EN of the UxCON2 register will need to be set or cleared accordingly. After the data transmission/reception is complete, the module will return to the Idle state until the UxP1 register is written again. Any writes to the UxP1 register before the master process is complete will not create a new master process and will instead set the Transmit Write Error (TXWRE) bit of the UxFIFO register.