Look-Ahead Operations (Precharge and Auto-Precharge)

The DDR controller contains logic that precharges and auto-precharges based on upcoming read or write requests pending in the queue. The DDR subsystem looks into the queue and determines whether a request requires a precharge command before a read or write command can be issued. When such a requirement is detected, the subsystem issues the necessary precharge command on the SDRAM bus to maximize the data bandwidth efficiency. The look-ahead auto-precharge logic issues an auto-precharge command (concurrent with the current read or write command) when it detects that a precharge to that bank is necessary for a read or write request currently pending in the command queue.

Notes:
  1. 1.By default, Look-Ahead operations are not enabled, they can be enabled using DDR configurator. Look-Ahead operations effect the timing closure of the DDR subsystem.
  2. 2.SDRAM commands are issued only for every 4 memory clocks, The timing diagrams shown in this document are only for general understanding and do not illustrate the same.

The following figure shows a sample timing diagram of the look-ahead precharge feature. In this sequence, two requests are issued to two different banks. The first request is issued to a bank that only requires an activate command. The second request is issued to a bank that requires a precharge and an activate. The first activate corresponding to the first request is issued at clock cycle 2. The write command associated with the first request does not occur until clock cycle 5 due to the tRCD requirement of SDRAM devices.

Figure 1. Sample Read and Write Sequence With Look Ahead Precharge (Full Wave)
Figure 2. Sample Read and Write Sequence With Look Ahead Precharge (Zoomed)

The following points summarize a read-write sequence with Look-Ahead Precharge:

  1. 1.The L_W_REQ signal is asserted along with the L_ADDR signal, and the L_B_SIZE signal is set to 32.
  2. 2.The L_W_REQ signal is deasserted, indicating no other write requests are required.
  3. 3.As a result of the write request, the subsystem asserts the row address (A), bank address (BA), and chip select (CS_N) using the Look-Ahead Precharge command to open the bank at the requested row.
  4. 4.L_D_REQ transitions a clock cycle after which, the values that enable the Look-Ahead Precharge appear on the COMMAND signal as highlighted in Figure 2.
  5. 5.The subsystem issues the write command with a column address corresponding to the request.
  6. 6.The subsystem issues the next write command with the corresponding column address.
  7. 7.The written data begins to appear on the SDRAM bus on the DQ lines.
  8. 8.L_W_VALID is asserted, and written data appears on the native interface, and then L_W_VALID is deasserted.
  9. 9.The read operation follows the same sequence.

The following figure shows a sample timing diagram without the Look-Ahead Precharge feature.

Figure 3. Sample Read and Write Sequence Without Look Ahead Precharge (Full Wave)
Figure 4. Sample Read and Write Sequence Without Look Ahead Precharge (Zoomed)

The following points summarize a read-write sequence without Look-Ahead Precharge:

  1. 1.The L_W_REQ signal is asserted along with the L_ADDR signal, and the L_B_SIZE signal is set to 32.
  2. 2.The L_W_REQ signal is deasserted, indicating no other write requests are required.
  3. 3.As a result of the write request, the subsystem asserts the row address (A), bank address (BA), and chip select (CS_N) using the look-Ahead Precharge command to open the bank at the requested row.
  4. 4.L_D_REQ transitions a clock cycle after which, the values that disable the Look-Ahead Precharge appear on the COMMAND signal as highlighted in Figure 4.
  5. 5.The subsystem issues the write command with a column address corresponding to the request.
  6. 6.The subsystem issues the next write command with the corresponding column address.
  7. 7.The written data begins to appear on the SDRAM bus on the DQ lines.
  8. 8.L_W_VALID is asserted, and written data appears on the native interface, and then L_W_VALID is deasserted.
  9. 9.The read operation follows the same sequence.