DQS Gate Training

After the fourth step, Controller initiates the DQS Gate Training in the following sequence:

  1. 1.The controller initiates the DQS Gate Training by asserting DFI_RDLVL_GATE_EN. The controller must write 0 to MR1 (for DDR3/4)/MR2 (for LPDDR3) bit 7 by issuing the MRS command for disabling the Write Leveling of Step 4.
  2. 2.The controller writes 1 to MR3 bit 2 for enabling data on DQ bus flow from MPR (Multi-Purpose Register) for DDR3 and DDR4 SDRAMs.
  3. 3.The controller must assert DFI_RDLVL_GATE_EN = 1 and wait for dfi_rdlvl_resp. After detecting DFI_RDLVL_GATE_EN = 1, the Training IP starts the DQS Gate Training algorithm.
  4. 4.The Training IP positions the DQS_GATE mask to enable READ_DQ and READ_DQS as shown in the following figure.
Figure 1. DQS Gate Training Conceptual View

When the DQS GATE Mask is positioned correctly, the read data matches the pattern selected in the MPR register. Then, the Training IP will assert DFI_RDLVL_RESP. After sampling DFI_RDLVL_RESP = 1, the controller can de-assert DFI_RDLVL_GATE_EN = 0. For DDR3/4, the controller must write 0 to MR3 bit 2 for restoring normal data flow on the DQ bus. (MR3 bit 2 = 0 > Normal Data flow; MR3 bit 2 = 1 > Data flow from MPR)

Otherwise, DQS strobe pulses will be missing and the read data will not match the pattern selected in the MPR register.

Note: For DDR3/4, the controller must issue regular READ commands to read the data from MPR. For LPDDR3, the controller must issue mode register read to MR32 or MR40. The time between reads must at least be 62 SYS_CLK cycles long so that the Training IP can stabilize. The DFI READ time during the MPR reads must be the same as the normal data read operations. During the DQS Gate training, the timing of DFI_RDDATA_VALID is not trained.