DDR3

The following are the guidelines for connecting the device to the DDR3 memory:

DDR3 data nets have dynamic ODT built into the controller and SDRAM. The configurations are 60 Ω, and 120 Ω. DQ lines do not need VTT termination. However, VTT termination resistors need to be placed at the end of address and control lines on the PCB.
Characteristic impedance: Z_O is typically 50 Ω, and Zdiff (differential) is 100 Ω.

The following table lists the DDR3 memory interface features supported in PolarFire devices.

Table 1. Interfaces Supported in DDR3 Memory Devices
Interface	DDR3
Voltage	1.5 V
I/O standard	SSTL_15
Data rate	1333 MT/S-HSIO and 1066 MT/S-GPIO
Termination	ODT for data group; VTT termination for address, command, and control
Routing topology (CK, ADDR/CMD, and CONTROL)	Fly-by
Data transmission	Point-to-point

The following figure shows the connectivity between DDR3 devices and PolarFire FPGAs.

Figure 1. DDR3 Interface Example