Write Calibration

The write leveling described in step 4 addresses only timing. It does not address latency. In the fly-by topology, there is a latency from the first DRAM device to the last DRAM device. Write calibration is not defined in the DFI Specification. This implementation of Write calibration is specific to PolarFire and PolarFire SoC designs.

Correcting for latency is accomplished by pushing both DQ and DQS by a full clock cycle (memory clock, CK0/CK0_N). The Training IP handles the Write calibration. The Training IP writes and reads known patterns through the controller and pushes DQ/DQS by a full clock cycle until Writes and Reads match. This step is also called as coarse correction because DQS is pushed by a full clock cycle. The Write calibration is done on a per byte lane basis.

The Write calibration is handled by a group of signals called CAL_TRAINING interface.

After the completion of READ Data eye training (Step 6), the Training IP asserts the DFI_TRAINING_COMPLETE signal. The Write Calibration sequence is as follows.

  1. 1.Training IP issues TRAINING_COMPLETE.
  2. 2.Controller asserts CTRLR_READY_IN.
  3. 3.For DDR3/4, the controller writes to ‘MR3’ ‘0x0’ to restore normal data flow. This restores the DQ data flow in the normal mode.
  4. 4.Controller de-asserts CAL_L_BUSY (0x0). Training IP asserts CAL_SELECT (0x1, ~CAL_L_BUSY).
  5. 5.Training IP issues CAL_L_W_REQ to issue ‘WRITE’ Command.
  6. 6.Controller issues CAL_L_D_REQ one clock before Data required.
  7. 7.Training IP provides ‘CAL_L_DATAIN’ & ‘CAL_L_DM_IN’ in the following clock.
  8. 8.Controller issues ‘WRITE’ command on DFI to be written to DRAM.
  9. 9.After waiting for 19 SYS_CLK clock cycles, the Training IP issues CAL_L_R_REQ to issue ‘READ’ command.
  10. 10.Controller Reads Data from DRAM and presents it on ‘CAL_L_DATAOUT’ with ‘CAL_L_R_VALID’.
  11. 11.Training IP compares DATA written and read.
  12. 12.If DATA written and read do not match, Training IP pushes DQ/DQS by full clock cycle at a time, until DATA written matches DATA read.
  13. 13.Upon successful completion of this sequence, the Training IP asserts CTRLR_READY_OUT and de-asserts CAL_SELECT in the following clock.
  14. 14.Controller will de-assert CAL_L_BUSY (0x1) to indicate Write calibration complete.

The following figures show the Write calibration sequence.

Figure 1. Write And Read Of Known Patterns During Write Calibration
Figure 2. Write And Read Sequence During Write Calibration
Figure 3. Write Calibration Sequence
Figure 4. Write Calibration Complete