Clocking Structure

Both the DDR subsystem and the DDR PHY-only solution require a dedicated PLL to generate the clocks, which are then distributed throughout the subsystem using HS_IO_CLK routes, dedicated pads, and fabric clock routing. This PLL generates aligned clocks for all sub-blocks for smooth operation and synchronous communication with the user logic.

The PLL generates the following required clocks:

The HS_IO_CLK and REF_CLK clocks are generated with the same frequency and phase. The REF_CLK to SYS_CLK ratio is 4:1.

The following illustration shows the clocking structure of the DDR subsystem.

Figure 1. DDR Clocking Structure
Note: The dedicated clock output pad, CCC_xx_PLLy_OUTz, is selected depending on the DDR subsystem placement constraint, where xx = SE/NE/NW/SW, y = 0/1, and z = 0/1.