PHY Configurator

The PolarFire DDR PHY IP core is delivered with a configurator, which includes parameters like bus width, density, organization and frequency of operation. The port widths on DFI read and write interfaces depend on the DQ bus width selected for the design.

The following tables list the DFI read and write interfaces and their corresponding DQ bus width on the DRAM interface.

Table 1. DFI Port Widths Vs DRAM DQ Bus Width (16-bit Interface)
DFI Signal name Interface DRAM DQ Width Remarks
dfi_rddata_w0[31:0] READ DQ[15:0]

DQS[1:0]

DQS_N[1:0]

dfi_rddata_w* width is [31:0] for 16 bit DRAM interface.

(4 x 32 = 128 bit data transferred to controller in a single SYS_CLK)

dfi_rddata_w1[31:0]
dfi_rddata_w2[31:0]
dfi_rddata_w3[31:0]
dfi_rddata_valid_w0[1:0] dfi_rddata_valid width is 1:0 for two byte lanes.
dfi_rddata_valid_w1[1:0]
dfi_rddata_valid_w2[1:0]
dfi_rddata_valid_w3[1:0]
dfi_rddata_cs_n_p0** cs_n_p** width is 1. These signals are always asserted in the Libero SoC design
dfi_rddata_cs_n_p1**
dfi_rddata_cs_n_p2**
dfi_rddata_cs_n_p3**
dfi_rddata_en_p0[1:0]* *dfi_rddata_en_p* is 15:0. Out of this only 1:0 are used for two byte lanes.
dfi_rddata_en_p1[1:0]*
dfi_rddata_en_p2[1:0]*
dfi_rddata_en_p3[1:0]*
dfi_wrdata_p0[31:0] WRITE DQ[15:0]

DQS[1:0]

DQS_N[1:0]

dfi_wrdata_p* width is [31:0] for 16 bit DRAM interface.

(4 x 32 = 128 bit Data transferred from controller in a single SYS_CLK)

dfi_wrdata_p1[31:0]
dfi_wrdata_p2[31:0]
dfi_wrdata_p3[31:0]
dfi_wrdata_mask_p0[3:0] Data on dfi_wrdata is valid only when wrdata_mask is ‘0’

(4bytes of wrdata[31:0] have 4 bits of mask)

dfi_wrdata_mask_p1[3:0]
dfi_wrdata_mask_p2[3:0]
dfi_wrdata_mask_p3[3:0]
dfi_wrdata_cs_n_p0** cs_n_p** width is 1. These signals are always asserted in Libero SoC design
dfi_wrdata_cs_n_p1**
dfi_wrdata_cs_n_p2**
dfi_wrdata_cs_n_p3**
dfi_wrdata_en_p0[1:0]* *dfi_wrdata_en_p* is 15:0. Out of this only 1:0 are used for two byte lanes.
dfi_wrdata_en_p1[1:0]*
dfi_wrdata_en_p2[1:0]*
dfi_wrdata_en_p3[1:0]*
Table 2. DFI PORT WIDTH VS DRAM DQ BUS WIDTH – 32 BIT INTERFACE
DFI Signal name Interface DRAM DQ Width Remarks
dfi_rddata_w0[63:0] READ dfi_rddata_w* width is [63:0] for 32 bit DRAM interface.

(4 x 64 = 256 bit Data transferred to controller in a single SYS_CLK)

dfi_rddata_w1[63:0]
dfi_rddata_w2[63:0]
dfi_rddata_w3[63:0]
dfi_rddata_valid_w0[3:0] dfi_rddata_valid width is 3:0 for four byte lanes.
dfi_rddata_valid_w1[3:0]
dfi_rddata_valid_w2[3:0] DQ[31:0]
dfi_rddata_valid_w3[3:0] DQS[3:0]
dfi_rddata_cs_n_p0** DQS_N[3:0] cs_n_p** width is 1. These signals are always asserted in Libero SoC design.
dfi_rddata_cs_n_p1**
dfi_rddata_cs_n_p2**
dfi_rddata_cs_n_p3**
dfi_rddata_en_p0[3:0]* *dfi_rddata_en_p* is 31:0. Out of this only 3:0 are used for four byte lanes.
dfi_rddata_en_p1[3:0]*
dfi_rddata_en_p2[3:0]*
dfi_rddata_en_p3[3:0]*
dfi_wrdata_p0[63:0] dfi_wrdata_p* width is [63:0] for 32 bit DRAM interface.

(4 x 64 = 256 bit Data transferred from controller in a single SYS_CLK)

dfi_wrdata_p1[63:0]
dfi_wrdata_p2[63:0]
dfi_wrdata_p3[63:0]
dfi_wrdata_mask_p0[7:0] Data on dfi_wrdata is valid only when wrdata_mask is ‘0’

(8 bytes of wrdata[63:0] have 8 bits of mask)

dfi_wrdata_mask_p1[7:0]
dfi_wrdata_mask_p2[7:0]
dfi_wrdata_mask_p3[7:0] DQ[31:0]
dfi_wrdata_cs_n_p0** WRITE DQS[3:0] cs_n_p** width is 1. These signals are always asserted in Libero SoC design
dfi_wrdata_cs_n_p1** DQS_N[3:0]
dfi_wrdata_cs_n_p2**
dfi_wrdata_cs_n_p3**
dfi_wrdata_en_p0[3:0]* *dfi_wrdata_en_p* is 31:0. Out of this only 3:0 are used for four byte lanes.
dfi_wrdata_en_p1[3:0]*
dfi_wrdata_en_p2[3:0]*
dfi_wrdata_en_p3[3:0]*

The configuration of the controller and the DDR PHY must be matched. For example, if the controller is configured for 32-bit DQ width, PHY also must be configured for the 32-bit DQ width.

The DDR3 PHY is instantiated by selecting the Generate PHY Only check box in the PolarFire DDR3 configurator > General Tab settings. When this check box is selected as shown in the following figure, the remaining tabs are grayed out because these settings are pertaining to the controller.

Figure 1. DDR3 PHY-Only Configurator

The following parameters are configurable: