DDR4 Optimization Guidelines

The following points provides guidance in selecting the proper speed bin memory component when using the PolarFire DDR PHY with the DDR4 Controller IP from Libero SoC:

1. 1.The PolarFire DDR4 interface can operate up to 1600 Mbps. To achieve maximum efficiency at this speed, a 2400 Mbps speed bin DDR4 SDRAM must be used. Maximum efficiency is achieved with the tCCD_L = 4 (4 clock cycles) parameter setting. The following calculations can be used as examples to determine the memory component speed bin to be selected when running at a user's desired memory clock rate:
   • For DDR4-2400 memory components, tCCD_L must be ≥ 5 ns.
     • 4clock cycles * (1/800 MHz) = 5 ns, hence, an 800 MHz memory clock can be used to achieve
1600 Mbps data rate.
   • For DDR4-2133 memory components, tCCD_L must be ≥ 5.355 ns
     • 4clock cycles * (1/746 MHz) = 5.36 ns, hence, a 746 MHz memory clock can be used to achieve 1492 Mbps data rate.
   • For DDR4-1866 memory components, tCCD_L must be ≥ 5.355 ns
     • 4 clock cycles * (1/746 MHz) = 5.36 ns, hence, a 746 MHz memory clock can be used to achieve 1492 Mbps data rate.
2. 2.tCCD_L delay values are obtained from Micron's 8Gb_DDR4_SDRAM datasheet.
3. 3.The tCCD_L delay values are the same for DDR4-2133 and DDR4-1866.
4. 4.In the above calculations, a slower memory clock can also be used.

These examples may not apply if the embedded DDR PHY is interfaced to a proprietary DDR Controller IP. In this case, the user must develop appropriate set of optimized parameters.