DDR PHY-Only Solution Integration

This section describes how to integrate third party DDR memory controllers with PolarFire DDR PHY. The PHY top-level behavior on both DFI and DRAM interfaces are detailed in this section.

The PolarFire DDR PHY-only solution is DFI 3.1 complaint and supports DDR3, DDR4, and LPDDR3.

The PolarFire DDR PHY-only solution includes a PLL (CCC – Clock Conditioning circuit) and an integrated PHY as shown in Figure 2. The integrated PHY includes I/O lanes and training logic, I/O lanes are used for command/data.

The following figure shows the top-level I/O of the DDR PHY. The signals are grouped and color coded for easy visualization.

Figure 1. DDR3 PHY-Only Top-Level I/O

As shown in the previous figure, DFI signals DFI_INIT_START and DFI_INIT_COMPLETE are part of the status interface according to the DFI 3.1 specification. These signals are shown as part of the training interface because the PHY performs the clock training from SYS_CLK to HSIO_CLK and from HSIO_CLK to REF_CLK during the initialization.