Data Ordering with Non-Aligned Starting Addresses

For write and read requests with a starting address aligned to the programmed burst length, data flow to and from SDRAM devices is always sequential. Each successive data phase within a burst corresponds to a higher address value. If the starting address is not aligned to the programmed burst length, the data will not be sequential. At a minimum, a wrap occurs, because only the locations within a burst range can be accessed with the exact ordering depending on the lower three bits of the address. The multi-burst capability automatically deals with these issues, off-loading the burden from the user logic.