Using PDC

To select the DDR subsystem location, add the following PDC constraint to the floor planner constraints:

set_location -inst_name <memory component inst name> -location <edge>_<anchor>

For example, set_location –inst_name {DDR3_TOP/DDR3_0} –location {NORTH_NE}.

The number of I/Os per bank varies from package to package; therefore, the maximum DDR memory width supported by each bank is not same for all PolarFire and PolarFire SoC FPGA packages. For more information, see the respective user guides as follows: