DDR Subsystem Ports

The Fabric DDR subsystem ports are categorized into the following groups:

AXI3/4 slave interface signals—required when the DDR subsystem is configured in AXI3/4 mode. An AXI master is implemented in the FPGA fabric to perform DDR memory transactions by interfacing with the DDR subsystem.
Native interface signals—required when the DDR subsystem is configured in native interface mode. To perform DDR memory transactions, custom logic must be implemented in the FPGA fabric to interface with the DDR subsystem. Logic connected to the native interface must operate synchronously with the SYS_CLK.
Refresh controls—required for user-initiated refresh control.
ZQ controls—required for user-initiated ZQ calibration control.
RE-INIT controls—required for re-initializing DDR memories.
SDRAM interface signals—required for connecting to the DDR SDRAM.

The following figure shows the DDR subsystem ports.

Figure 1. Fabric DDR Subsystem Ports

In addition to ports shown in the preceding figure, the Fabric DDR subsystem also has some generic ports, see the following table.

Table 1. Generic Signals
Signal Name	Direction	Description
SYS_CLK	Output	Clock for user logic generated by the embedded PLL. All native interface signals are synchronous to this clock. Always on the global clock network.
SYS_RESET_N	Input	Active-low asynchronous system reset. SYS_RESET_N must be generated by ANDing the DEVICE_INIT_DONE and BANK_X_CALIB_STATUS signals of the PF_INIT_MONITOR IP¹. BANK_X refers to the BANK where Fabric DDR subsystem is placed.
PLL_REF_CLK	Input	Reference clock to the PLL.
PLL_LOCK	Output	Lock signal generated by the PLL to indicate that the PLL is locked on to the PLL_REF_CLK signal.
CTRLR_READY	Output	Signal that is deasserted when in reset or after CTRLR_INIT is asserted, then asserted after initialization and training sequences (if applicable) are completed.
ALERT_N (ERR_OUT_N)	Input	This signal is asserted by the DDR memory when it detects a CA parity error or a CRC error. It is an input from DDR3 RDIMM or LRDIMM, and DDR4 components or DIMMs.
stat_ca_parity_error	Output	This signal is asserted when an assertion is detected on the ALERT_N pin. Each occurrence of a write CRC error or CA parity error causes the assertion of the ALERT_N pin. The value is cleared on read.

Note:

1.For more information about the PF_INIT_MONITOR IP, see PolarFire FPGA and PolarFire SoC FPGA Device Power-Up and Resets User Guide.

The DDR Controller complies with the AXI3/4 protocol. The AXI3/4 slave interface provides the following features:

Supports all AXI allowed burst sizes, types, and lengths.
Handles all AXI wrapping conditions.
Supports 64-bit, 128-bit, 256-bit, and 512-bit AXI interfaces.

For more information about the AXI3/4 protocol, see the AMBA AXI and ACE Protocol Specification.

The following table lists the AXI3/4 slave interface signals. All AXI interface signals are active-high and are synchronous to SYS_CLK.

Table 2. AXI3/4 Slave Interface Signals
Signal Name	Direction	Description
Write Address Channel
AXI0_AWID[X-1:0]²	Input	Write address ID.
AXI0_AWADDR[31:0]	Input	Write address.
AXI0_AWLEN[M:0]	Input	Burst length. M = 7 for AXI4 IF and  M = 3 for AXI3 IF.
AXI0_AWSIZE[2:0]	Input	Burst size.
AXI0_AWBURST[1:0]	Input	Burst type.
AXI0_AWLOCK[1:0]	Input	Lock type.Not supported.
AXI0_AWCACHE[3:0]	Input	Memory type. Not supported.
AXI0_AWPROT[2:0]	Input	Protection type. Not supported.
AXI0_AWVALID	Input	Write address valid.
AXI0_AWREADY	Output	Write address ready.
Write Data Channel
AXI0_WID[X-1:0]	Input	Write ID tag. Supported only in AXI3.
AXI0_WDATA[N-1:0]¹	Input	Write data.
AXI0_WSTRB[N/8 - 1:0]¹	Input	Write strobes.
AXI0_WLAST	Input	Write last.
AXI0_WVALID	Input	Write valid.
AXI0_WREADY	Output	Write ready.
Write Response Channel
AXI0_BID[X-1:0]	Output	Response ID tag.
AXI0_BRESP[1:0]	Output	Write response.
AXI0_BVALID	Output	Write response valid.
AXI0_BREADY	Input	Response ready.
Read Address Channel
AXI0_ARID[X-1:0]²	Input	Read address ID.
AXI0_ARADDR[31:0]	Input	Read address.
AXI0_ARLEN[M:0]	Input	Burst length. M = 7 for AXI4 IF and  M = 3 for AXI3 IF.
AXI0_ARSIZE[2:0]	Input	Burst size.
AXI0_ARBURST[1:0]	Input	Burst type.
AXI0_ARLOCK[1:0]	Input	Lock type. Not supported.
AXI0_ARCACHE[3:0]	Input	Memory type. Not supported.
AXI0_ARPROT[2:0]	Input	Protection type. Not supported.
AXI0_ARVALID	Input	Read address valid.
AXI0_ARREADY	Output	Read address ready.
Read Data Channel
AXI0_RID[X-1:0]²	Output	Read ID tag.
AXI0_RDATA[N-1:0]	Output	Read data.
AXI0_RRESP[1:0]	Output	Read response.
AXI0_RLAST	Output	Read last.
AXI0_RVALID	Output	Read valid.
AXI0_RREADY	Input	Read ready.

Notes:

1. N can be configured as 64,128, 256, or 512 using the Fabric DDR subsystem configurator.
2. ‘X’ can be configured between 1 to 8 using the Fabric DDR Configurator.

The following table lists the native interface signals. All control signals are active-high and are synchronous to SYS_CLK.

Table 3. Native Interface Signals
Signal Name	Direction	Description
L_ADDR[38:0]	Input	Native interface address sizes: DDR4 = 39 bits, DDR3 = 36 bits, and LPDDR3 = 36 bits
L_B_SIZE[10:0]	Input	Native interface burst length in terms of bytes. It must be in multiples of the native interface bus width.
L_R_REQ	Input	Native interface read request.
L_W_REQ	Input	Native interface write request.
L_AUTO_PCH	Input	When asserted along with L_R_REQ or L_W_REQ, causes the command to be issued as read with auto-precharge and write with auto-precharge, respectively.
L_BUSY	Output	Specifies that the subsystem is busy and is not accepting new requests. A command is accepted on any clock cycle where L_R_REQ or L_W_REQ is set, and L_BUSY is low. If L_BUSY is high when L_R_REQ or L_W_REQ is set, the request may be kept asserted (along with the desired L_ADDR, L_B_SIZE and L_AUTO_PCH values) until L_BUSY goes low.
L_D_REQ	Output	Requests data on the native interface write data bus (L_DATAIN) during a write transaction. Asserts one clock cycle prior to when data is required.
L_D_REQ_LAST_P0	Output	Requests the last data on the native interface write data bus This signal is used along with L_D_REQ
L_R_VALID	Output	Data-valid indication for data on the native interface read data bus (L_DATAOUT).
L_R_VALID_LAST_P0	Output	Data-valid indication for the last data on the native interface read data bus This signal is used along with L_R_VALID
L_DATAIN[N:0]	Input	Input data bus. This data bus is eight times the width of the SDRAM device data bus. Memory width (bits): 16, 32, 64. Input data bus (bits): 128, 256, 512.
L_DATAOUT[N:0]	Output	Output data bus. This data bus is twice the width of the SDRAM device data bus. Memory width (bits): 16, 32, 64. Output data bus (bits): 128, 256, 512.
L_DM_IN[N:0]	Input	Individual byte masks during data write. Memory width (bits): 16, 32, 64. Data mask bus (bits): 16, 32, 64.

The following table lists the refresh control signals. To expose these signals, select the Enable User Refresh Controls check box from DDR3/LPDDR3 configurator > Controller tab > Efficiency.

Table 4. Refresh Control Signals
Signal Name	Direction	Description
L_REF_REQ	Input	User-initiated refresh control. Causes a refresh command to be issued at the next opportunity. This signal is only used when manual control of refresh is desired. The DDR Configurator provides an option (Enable User Refresh Controls) to expose the user-initiated refresh control (L_REF_REQ) signal. tREFI parameter in the DDR Configurator specifies the period between refreshes.
L_REF_ACK	Output	Refresh acknowledge. Asserted for one clock cycle when a refresh command is being issued. Typically used to determine when a refresh was last issued in user-controlled refresh. Can be ignored when the subsystem is automatically generating refreshes.

The following table lists the ZQ calibration control signals. To expose these signals, enable User ZQ Calibration Controls in the DDR Configurator Memory Timing tab.

Table 5. ZQ Calibration Control Signals
Signal Name	Direction	Description
L_ZQ_CAL_REQ	Input	Causes user-initiated ZQCS or ZQCL requests to be issued at the next opportunity. The ZQCS or ZQCL are issued to the ranks corresponding to the asserted bits. ZQ calibration can be initiated either automatically or manually. The DDR Configurator provides an option to enable automatic ZQ calibration and to set the automatic ZQ calibration period.
L_ZQ_CAL_ACK	Output	ZQ calibration acknowledge. Asserted for a single clock cycle when a ZQ calibration command is issued to memory devices. Used for ZQ calibrations initiated by asserting the L_ZQ_CAL_REQ signal.

The following table describes the reinitialization control signal. To expose this signal, enable RE-INIT Controls in the DDR Configurator Controller tab.

Table 6. Reinitialization Control Signal
Signal Name	Direction	Description
CTRLR_INIT	Input	Causes the subsystem to reissue the initialization sequence to the SDRAM. The initialization begins when a low-to-high transition is detected on the input. The controller always issues the initialization sequence (including the startup delay) after a reset, regardless of this signal’s state. If run-time reinitialization is not required, the signal can be tied low.

The following table lists the ECC status signals.

Table 7. ECC Status Signals
Signal Name	Direction	Description
ECC_ERROR_1BIT	Output	Active when a 1-bit error is detected on the data being presented on the AXI RDATA/L_DATAOUT port.
ECC_ERROR_2BIT	Output	Active when a 2-bit error is detected on the data being presented on the AXI RDATA/L_DATAOUT port.
ECC_ERROR_POS[6:0]	Output	Indicates bit position of the error in a 64-bit data output for a 1-bit error.

The following table lists the SDRAM interface signals.

Table 8. SDRAM Interface Signals
Signal Name	Direction	Description
CK	Output	Differential clock pair forwarded to SDRAM.
CK_N	Output	Differential clock pair forwarded to SDRAM.
RESET_N	Output	SDRAM reset. Supported only for DDR3 and DDR4.
A[15:0]	Output	Address bus. Sampled during the active, precharge, read, and write commands. Also provides the mode register value during MRS commands. Bus width for LPDDR3 is 10 bits, DDR3 is 16 bits, and DDR4 is 14 bits.
BA[2:0]	Output	Bank address. Sampled during active, precharge, read, and write commands to determine which bank the command is to be applied to. Supported only for DDR3 and DDR4. For DDR4, bus width is 2 bits. For DDR3, bus width is 3 bits.
BG[1:0]	Output	DDR bank group address for DDR4 only.
CS_N	Output	SDRAM chip select.
CKE	Output	SDRAM clock enable. Held low during initialization to ensure SDRAM DQ and DQS outputs are in the hi-Z state.
RAS_N	Output	SDRAM row address strobe command. Supported only for DDR3 and DDR4.
CAS_N	Output	SDRAM column access strobe command. Supported only for DDR3 and DDR4.
WE_N	Output	SDRAM write-enable command. Supported only for DDR3 and DDR4.
ODT	Output	On-die termination control. ODT is asserted during reads and writes according to the ODT activation settings in the DDR Configurator.
PAR	Output	Command and address parity output. Supported only for DDR4.
ALERT_N (ERR_OUT_N)	Input	It is asserted by the DDR memory when it detects a CA parity error or a CRC error. It is an input from DDR3 RDIMM or LRDIMM, and DDR4 components or DIMMs.
DQ	Bidirectional	SDRAM data bus. Supports 16-bit, 32-bit, 39-bit, 64-bit, and 72-bit DDR SDRAM data buses.
DM/DM_N	Output	Write data mask. DM for DDR3/LPDDR3 and DM_N for DDR4.
DQS	Bidirectional	Strobes data into the SDRAM devices during writes and into the DDR subsystem during reads.
DQS_N	Bidirectional	Complimentary DQS.
SHIELD	Output	Pads must be connected to ground. They are placed between the data lanes for improving signal integrity.