SDRAM Writes

SDRAM writes are requested in the native interface by asserting the L_W_REQ signal high, and by driving the starting address and the burst size on the L_ADDR and L_B_SIZE signals respectively. A write can be requested with auto-precharge by asserting the L_AUTO_PCH signal along with the L_W_REQ signal.

The following are the rules for write requests in the native interface:

• A write is accepted by the subsystem on any clock cycle where the L_W_REQ signal is asserted while the L_BUSY signal is deasserted. After L_BUSY is deasserted by the controller, L_W_REQ may remain asserted to request a follow-on write transaction. L_W_REQ may remain asserted over any number of clock periods to generate any number of cascaded write requests.
• The values of the L_ADDRL_B_SIZE, and L_AUTO_PCH signals are captured when the L_BUSY signal is low. It is acceptable to permanently tie the L_B_SIZE and L_AUTO_PCH signals to fixed values.
• The L_W_REQ signal cannot be asserted while the L_R_REQ signal is asserted.
• The data request (L_D_REQ) signal is asserted one clock prior to the data signal at the L_DATAIN bus and the subsystem masks the information at the L_DM_IN bus.
• The timing relationship between an initial L_W_REQ, L_D_REQ, and L_BUSY or between L_BUSY assertions and de-assertions as a result of multiple cascaded writes varies depending on the status of the banks being accessed, the configuration port settings, and the refresh and initialization status.