The REF_CLK, HS_IO_CLK, HS_IO_CLK_270, and SYS_CLK clocks generated using the dedicated PLL require timing constraints for synthesis, place and route, and timing verification. To generate these timing constraints, select the Timing tab in Constraint Manager, and click Derive Constraints as shown in the following figure.
Figure 1. Constraint Manager—Derive Constraints Tab
When prompted, click Yes to apply the derived constraints for synthesis, place and route, and timing verification.