The following are the guidelines for connecting the device to the LPDDR3 memory:
- LPDDR3 data nets have dynamic ODT built into the controller and SDRAM. The configurations are 120 Ω and 240 Ω.
- DQ lines do not need VTT termination.
- The characteristic impedance, Zo is typically 50 Ω, and Zdiff (differential) is 100 Ω.
The following table lists the LPDDR3 memory interface features supported in PolarFire SoC devices.
| Interface | LPDDR3 |
|---|---|
| Voltage | 1.2 V |
| I/O standard | HSUL-12 |
| Data rate | 1333 MT/S-HSIO |
| Termination | ODT for data group |
| Routing topology | Point to point |
The following figure shows the connectivity between LPDDR3 devices and PolarFire SoC FPGAs.
Figure 1. LPDDR3 Interface Example
