Revision History

The revision history table describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Revision Date Description
B 11/2021 The following is a summary of the changes made in this revision:
  • Updated the clock frequency value of PolarFire Octal DDR PHY IP from 200 MHz to 250 MHz. See Octal DDR PHY-Only Solution and Table 1.
  • Updated the description of the output signal DOFF_N of the QDR Controller, see Port List.
  • Added RTL_Fast simulation information for QDR memory, see Configuring QDR Memory Controller IP and RTL_Fast Simulation.
  • Updated Figure 1 to show the latest configuration parameter Enable Differential DQS and added this configuration parameter to Table 1.
  • Added the ALERT_N signal and updated the description of the stat_ca_parity_error signal in Table 1.
  • Updated the description of the ALERT_N signal in Table 8.
  • Added the information about the Memory Format and Enable Parity/Alert options in General Options.
A 08/2021 The first publication of this document. This user guide was created by merging the following documents:
  • UG0676: PolarFire FPGA Memory Controller User Guide
  • UG0906: PolarFire SoC FPGA Memory Controller User Guide

For more information, see Table 1 and Table 2 respectively.

The following revision history table describes the changes that were implemented in the UG0676: PolarFire FPGA Memory Controller User Guide document. The changes are listed by revision.

Note: UG0676: PolarFire FPGA Memory Controller User Guide document is now obsolete and the information in the document has been migrated to PolarFire® FPGA and PolarFire SoC FPGA Memory Controller User Guide.
Table 1. Revision History of UG0676: PolarFire FPGA Memory Controller User Guide
Revision Date Description
Revision 8.0 04/21

The following is a summary of the changes made in this revision.

  • Updated that the DDR Controller complies with the AXI3/4 protocol.
  • Added DDR4 Additional Controller Options.
  • Added DDR4 Optimization Guidelines.
  • Added the prerequisite of setting VDDI and VREF before placing the DDR subsystem.
  • Removed DQ bit swapping information because it is not supported.
  • Added information about the minimum operating frequency of LPDDR3.
  • Updated for Libero SoC v2021.1.
Revision 7.0 10/20

The following is a summary of the changes made in this revision.

  • Added information about Octal DDR PHY-Only Solution.
  • Updated support for ECC at maximum width for various device variants.
  • Added brief information about SmartDebug capability of displaying DDR training data.
  • Updated for Libero SoC v12.5.
Revision 6.0 05/20

The following is a summary of the changes made in this revision.

  • Updated the description of the QDR output port DOFF_N.
  • Updated the QDR Training information.
  • Updated QDR related information for Burst of 2.
Revision 5.0 04/19

The following is a summary of the changes made in this revision.

  • Updated the document for Libero SoC v12.0.
  • Added simulated timing waveforms for write and read sequence with and without lookahead precharge.
  • Added simulated timing waveforms for sample multi-burst write and read sequence.
  • Added simulated timing waveforms for sample SDRAM write and read sequence.
  • Updated the information about the DQ bit swapping supported.
  • Updated the table that lists the Write Data to Write Strobe Mapping for QDR x36 mode.
  • Added tables that list the Write Data to Write Strobe Mapping for QDR x18 and x9 modes.
  • Updated “Burst of 2 local interface timing” and “Burst of 4 local interface timing” diagrams in QDR Memory Controller.
  • Updated the QDR simulation options.
  • Added information about BFM simulation.
  • Added L_D_REQ_LAST_P0 and L_R_VALID_LAST_P0 signals in “Native Interface Signals” table.
Revision 4.0 09/18

The following is a summary of the changes made in this revision.

  • The document was updated for Libero SoC PolarFire v2.3.
  • Added information about the DDR PHY-only solution.
  • Removed the VREFDQ leveling step from the initialization sequence of DDR3 and DDR4.
Revision 3.0 04/18

The following is a summary of the changes made in this revision.

  • Updated the title of the document and added the QDR memory controller information. Now, both DDR and QDR information is available in this document.
  • Updated the Libero SoC PolarFire version to v2.1 throughout the document.
  • Updated the DDR3 and DDR4 resource utilization data.
  • Updated the information about connectivity between DDR3 and PolarFire devices.
  • Updated the information about the native interface signals L_DATAIN[N:0], L_DATAOUT[N:0], and L_DM_IN[N:0].
  • Updated the data widths and I/O standard information for various types of memories.
  • Added the information about the simulation options available in the DDR3 configurator.
  • Updated the DDR3 and DDR4 parameters for PolarFire devices.
  • Updated the information about the standard LPDDR3 and DDR3 device configurations.
  • Added the DDR3, LPDDR3, and DDR4 layout guidelines.
  • Added the list of DDR placement location for each device package.
  • Removed the instances that mention the LPDDR2 support throughout the document.
Revision 2.0 06/17

The following is a summary of the changes made in this revision.

  • Information about DDR memory interface data lanes was updated.
  • Information about training logic was updated.
  • Information about diagnostic options was updated.
  • Information about physical constraints of the DDR subsystem was updated.
  • Information about accessing DDR Subsystem using the native interface was updated.
Revision 1.0 02/17 The first publication of UG0676: PolarFire FPGA Memory Controller User Guide.

The following revision history table describes the changes that were implemented in the UG0906: PolarFire SoC FPGA Memory Controller User Guide document. The changes are listed by revision.

Note: UG0906: PolarFire SoC FPGA Memory Controller User Guide document is now obsolete and the information in the document has been migrated to PolarFire® FPGA and PolarFire SoC FPGA Memory Controller User Guide.
Table 2. Revision History of UG0906: PolarFire SoC FPGA Memory Controller User Guide
Revision Date Description
Revision 3.0 04/21

The following is a summary of the changes made in this revision.

  • Updated that DDR Controller complies with the AXI3/4 protocol.
  • Added DDR4 Additional Controller Options.
  • Added DDR4 Optimization Guidelines.
  • Added the prerequisite of setting VDDI and VREF before placing the DDR subsystem.
  • Removed the DQ bit swapping information because it is not supported.
  • Updated for Libero SoC v2021.1.
Revision 2.0 09/20 Updated for Libero SoC v12.5.
Revision 1.0 04/20 The first publication of the UG0906: PolarFire SoC FPGA Memory Controller User Guide.